Lines Matching +full:6 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 Microchip Technology Inc.
14 /* 0 - Operation */
43 #define PME_ENABLE BIT(1)
44 #define PME_POLARITY BIT(0)
48 #define SW_GIGABIT_ABLE BIT(6)
49 #define SW_REDUNDANCY_ABLE BIT(5)
50 #define SW_AVB_ABLE BIT(4)
68 #define SW_QW_ABLE BIT(5)
74 #define LUE_INT BIT(31)
75 #define TRIG_TS_INT BIT(30)
76 #define APB_TIMEOUT_INT BIT(29)
85 /* 1 - Global */
87 #define SW_SPARE_REG_2 BIT(7)
88 #define SW_SPARE_REG_1 BIT(6)
89 #define SW_SPARE_REG_0 BIT(5)
90 #define SW_BIG_ENDIAN BIT(4)
91 #define SPI_AUTO_EDGE_DETECTION BIT(1)
92 #define SPI_CLOCK_OUT_RISING_EDGE BIT(0)
95 #define SW_ENABLE_REFCLKO BIT(1)
96 #define SW_REFCLKO_IS_125MHZ BIT(0)
100 #define SW_IBA_ENABLE BIT(31)
101 #define SW_IBA_DA_MATCH BIT(30)
102 #define SW_IBA_INIT BIT(29)
111 #define APB_TIMEOUT_ACKNOWLEDGE BIT(31)
123 #define SW_DRIVE_STRENGTH_24MA 6
130 #define SW_IBA_REQ BIT(31)
131 #define SW_IBA_RESP BIT(30)
132 #define SW_IBA_DA_MISMATCH BIT(14)
133 #define SW_IBA_FMT_MISMATCH BIT(13)
134 #define SW_IBA_CODE_ERROR BIT(12)
135 #define SW_IBA_CMD_ERROR BIT(11)
136 #define SW_IBA_CMD_LOC_M (BIT(6) - 1)
152 #define SW_IBA_RETRY_CNT_M (BIT(5) - 1)
154 /* 2 - PHY */
157 #define SW_PLL_POWER_DOWN BIT(5)
163 /* 3 - Operation Control */
166 #define SW_DOUBLE_TAG BIT(7)
167 #define SW_RESET BIT(1)
185 #define SW_SHAPING_CREDIT_ACCT BIT(1)
186 #define SW_POLICING_CREDIT_ACCT BIT(0)
190 #define SW_VLAN_ENABLE BIT(7)
191 #define SW_DROP_INVALID_VID BIT(6)
195 #define SW_RESV_MCAST_ENABLE BIT(2)
203 #define UNICAST_LEARN_DISABLE BIT(7)
204 #define SW_SRC_ADDR_FILTER BIT(6)
205 #define SW_FLUSH_STP_TABLE BIT(5)
206 #define SW_FLUSH_MSTP_TABLE BIT(4)
207 #define SW_FWD_MCAST_SRC_ADDR BIT(3)
208 #define SW_AGING_ENABLE BIT(2)
209 #define SW_FAST_AGING BIT(1)
210 #define SW_LINK_AUTO_AGING BIT(0)
214 #define SW_TRAP_DOUBLE_TAG BIT(6)
215 #define SW_EGRESS_VLAN_FILTER_DYN BIT(5)
216 #define SW_EGRESS_VLAN_FILTER_STA BIT(4)
234 #define LEARN_FAIL_INT BIT(2)
235 #define ALMOST_FULL_INT BIT(1)
236 #define WRITE_FAIL_INT BIT(0)
250 #define SW_UNK_UCAST_ENABLE BIT(31)
254 #define SW_UNK_MCAST_ENABLE BIT(31)
258 #define SW_UNK_VID_ENABLE BIT(31)
262 #define SW_NEW_BACKOFF BIT(7)
263 #define SW_CHECK_LENGTH BIT(3)
264 #define SW_PAUSE_UNH_MODE BIT(1)
265 #define SW_AGGR_BACKOFF BIT(0)
269 #define SW_BACK_PRESSURE BIT(5)
270 #define FAIR_FLOW_CTRL BIT(4)
271 #define NO_EXC_COLLISION_DROP BIT(3)
272 #define SW_JUMBO_PACKET BIT(2)
273 #define SW_LEGAL_PACKET_DISABLE BIT(1)
274 #define SW_PASS_SHORT_FRAME BIT(0)
278 #define SW_REPLACE_VID BIT(3)
284 #define SW_PASS_PAUSE BIT(3)
288 #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3)
292 #define SW_MIB_COUNTER_FLUSH BIT(7)
293 #define SW_MIB_COUNTER_FREEZE BIT(6)
307 #define SW_TOS_DSCP_REMARK BIT(1)
308 #define SW_TOS_DSCP_REMAP BIT(0)
345 #define SW_IGMP_SNOOP BIT(6)
346 #define SW_IPV6_MLD_OPTION BIT(3)
347 #define SW_IPV6_MLD_SNOOP BIT(2)
348 #define SW_MIRROR_RX_TX BIT(0)
352 #define SW_CLASS_D_IP_ENABLE BIT(31)
356 #define SW_NO_COLOR_S 6
365 #define PRIO_SCHEME_SELECT_S 6
369 #define UNICAST_VLAN_BOUNDARY BIT(1)
375 /* 4 - */
378 #define VLAN_VALID BIT(31)
379 #define VLAN_FORWARD_OPTION BIT(27)
395 #define VLAN_START BIT(7)
408 #define ALU_DIRECT_INDEX_M (BIT(12) - 1)
412 #define ALU_VALID_CNT_M (BIT(14) - 1)
414 #define ALU_START BIT(7)
415 #define ALU_VALID BIT(6)
416 #define ALU_DIRECT BIT(2)
424 #define ALU_RESV_MCAST_INDEX_M (BIT(6) - 1)
425 #define ALU_STAT_START BIT(7)
426 #define ALU_RESV_MCAST_ADDR BIT(1)
430 #define ALU_V_STATIC_VALID BIT(31)
431 #define ALU_V_SRC_FILTER BIT(30)
432 #define ALU_V_DST_FILTER BIT(29)
433 #define ALU_V_PRIO_AGE_CNT_M (BIT(3) - 1)
439 #define ALU_V_OVERRIDE BIT(31)
440 #define ALU_V_USE_FID BIT(30)
441 #define ALU_V_PORT_MAP (BIT(24) - 1)
445 #define ALU_V_FID_M (BIT(16) - 1)
460 #define HSR_INDEX_MAX BIT(9)
461 #define HSR_DIRECT_INDEX_M (HSR_INDEX_MAX - 1)
465 #define HSR_PATH_INDEX_M (BIT(4) - 1)
469 #define HSR_VALID_CNT_M (BIT(14) - 1)
471 #define HSR_START BIT(7)
472 #define HSR_VALID BIT(6)
473 #define HSR_SEARCH_END BIT(5)
474 #define HSR_DIRECT BIT(2)
482 #define HSR_V_STATIC_VALID BIT(31)
483 #define HSR_V_AGE_CNT_M (BIT(3) - 1)
485 #define HSR_V_PATH_ID_M (BIT(4) - 1)
511 #define HSR_V_SEQ_M (BIT(16) - 1)
513 /* 5 - PTP Clock */
516 #define PTP_STEP_ADJ BIT(6)
517 #define PTP_STEP_DIR BIT(5)
518 #define PTP_READ_TIME BIT(4)
519 #define PTP_LOAD_TIME BIT(3)
520 #define PTP_CLK_ADJ_ENABLE BIT(2)
521 #define PTP_CLK_ENABLE BIT(1)
522 #define PTP_CLK_RESET BIT(0)
539 #define PTP_RATE_DIR BIT(31)
540 #define PTP_TMP_RATE_ENABLE BIT(30)
550 #define PTP_802_1AS BIT(7)
551 #define PTP_ENABLE BIT(6)
552 #define PTP_ETH_ENABLE BIT(5)
553 #define PTP_IPV4_UDP_ENABLE BIT(4)
554 #define PTP_IPV6_UDP_ENABLE BIT(3)
555 #define PTP_TC_P2P BIT(2)
556 #define PTP_MASTER BIT(1)
557 #define PTP_1STEP BIT(0)
561 #define PTP_UNICAST_ENABLE BIT(12)
562 #define PTP_ALTERNATE_MASTER BIT(11)
563 #define PTP_ALL_HIGH_PRIO BIT(10)
564 #define PTP_SYNC_CHECK BIT(9)
565 #define PTP_DELAY_CHECK BIT(8)
566 #define PTP_PDELAY_CHECK BIT(7)
567 #define PTP_DROP_SYNC_DELAY_REQ BIT(5)
568 #define PTP_DOMAIN_CHECK BIT(4)
569 #define PTP_UDP_CHECKSUM BIT(2)
598 #define GPIO_IN BIT(7)
599 #define GPIO_OUT BIT(6)
600 #define TS_INT_ENABLE BIT(5)
601 #define TRIG_ACTIVE BIT(4)
602 #define TRIG_ENABLE BIT(3)
603 #define TRIG_RESET BIT(2)
604 #define TS_ENABLE BIT(1)
605 #define TS_RESET BIT(0)
620 #define TRIG_CASCADE_ENABLE BIT(31)
621 #define TRIG_CASCADE_TAIL BIT(30)
624 #define TRIG_NOW BIT(25)
625 #define TRIG_NOTIFY BIT(24)
626 #define TRIG_EDGE BIT(23)
635 #define TRIG_REG_OUTPUT 6
658 #define TS_EVENT_OVERFLOW BIT(16)
661 #define TS_DETECT_RISE BIT(7)
662 #define TS_DETECT_FALL BIT(6)
663 #define TS_DETECT_S 6
664 #define TS_CASCADE_TAIL BIT(5)
667 #define TS_CASCADE_ENABLE BIT(0)
706 #define TS_EVENT_NANOSEC_M (BIT(30) - 1)
711 (REG_TS_EVENT_1_NANOSEC - REG_TS_EVENT_0_NANOSEC)
720 #define DLR_SRC_PORT_UNICAST BIT(31)
729 #define DLR_RESET_SEQ_ID BIT(3)
730 #define DLR_BACKUP_AUTO_ON BIT(2)
731 #define DLR_BEACON_TX_ENABLE BIT(1)
732 #define DLR_ASSIST_ENABLE BIT(0)
752 #define DLR_TIMEOUT_WINDOW_M (BIT(22) - 1)
756 #define DLR_VLAN_ID_M (BIT(12) - 1)
776 #define HSR_DUPLICATE_DISCARD BIT(7)
777 #define HSR_NODE_UNICAST BIT(6)
780 #define HSR_LEARN_MCAST_DISABLE BIT(2)
789 #define HSR_LEARN_UCAST_DISABLE BIT(7)
790 #define HSR_FLUSH_TABLE BIT(5)
791 #define HSR_PROC_MCAST_SRC BIT(3)
792 #define HSR_AGING_ENABLE BIT(2)
801 #define HSR_WINDOW_OVERFLOW_INT BIT(3)
802 #define HSR_LEARN_FAIL_INT BIT(2)
803 #define HSR_ALMOST_FULL_INT BIT(1)
804 #define HSR_WRITE_FAIL_INT BIT(0)
808 #define HSR_ENTRY_INDEX_M (BIT(10) - 1)
809 #define HSR_FAIL_INDEX_M (BIT(8) - 1)
813 #define HSR_FAIL_LEARN_INDEX_M (BIT(8) - 1)
817 #define HSR_CPU_ACCESS_ENTRY_INDEX_M (BIT(8) - 1)
819 /* 0 - Operation */
832 #define PME_WOL_MAGICPKT BIT(2)
833 #define PME_WOL_LINKUP BIT(1)
834 #define PME_WOL_ENERGY BIT(0)
839 #define PORT_SGMII_INT BIT(3)
840 #define PORT_PTP_INT BIT(2)
841 #define PORT_PHY_INT BIT(1)
842 #define PORT_ACL_INT BIT(0)
849 #define PORT_MAC_LOOPBACK BIT(7)
850 #define PORT_FORCE_TX_FLOW_CTRL BIT(4)
851 #define PORT_FORCE_RX_FLOW_CTRL BIT(3)
852 #define PORT_TAIL_TAG_ENABLE BIT(2)
867 #define PORT_INTF_FULL_DUPLEX BIT(2)
868 #define PORT_TX_FLOW_CTRL BIT(1)
869 #define PORT_RX_FLOW_CTRL BIT(0)
873 /* 1 - PHY */
876 #define PORT_PHY_RESET BIT(15)
877 #define PORT_PHY_LOOPBACK BIT(14)
878 #define PORT_SPEED_100MBIT BIT(13)
879 #define PORT_AUTO_NEG_ENABLE BIT(12)
880 #define PORT_POWER_DOWN BIT(11)
881 #define PORT_ISOLATE BIT(10)
882 #define PORT_AUTO_NEG_RESTART BIT(9)
883 #define PORT_FULL_DUPLEX BIT(8)
884 #define PORT_COLLISION_TEST BIT(7)
885 #define PORT_SPEED_1000MBIT BIT(6)
889 #define PORT_100BT4_CAPABLE BIT(15)
890 #define PORT_100BTX_FD_CAPABLE BIT(14)
891 #define PORT_100BTX_CAPABLE BIT(13)
892 #define PORT_10BT_FD_CAPABLE BIT(12)
893 #define PORT_10BT_CAPABLE BIT(11)
894 #define PORT_EXTENDED_STATUS BIT(8)
895 #define PORT_MII_SUPPRESS_CAPABLE BIT(6)
896 #define PORT_AUTO_NEG_ACKNOWLEDGE BIT(5)
897 #define PORT_REMOTE_FAULT BIT(4)
898 #define PORT_AUTO_NEG_CAPABLE BIT(3)
899 #define PORT_LINK_STATUS BIT(2)
900 #define PORT_JABBER_DETECT BIT(1)
901 #define PORT_EXTENDED_CAPABILITY BIT(0)
911 #define PORT_AUTO_NEG_NEXT_PAGE BIT(15)
912 #define PORT_AUTO_NEG_REMOTE_FAULT BIT(13)
913 #define PORT_AUTO_NEG_ASYM_PAUSE BIT(11)
914 #define PORT_AUTO_NEG_SYM_PAUSE BIT(10)
915 #define PORT_AUTO_NEG_100BT4 BIT(9)
916 #define PORT_AUTO_NEG_100BTX_FD BIT(8)
917 #define PORT_AUTO_NEG_100BTX BIT(7)
918 #define PORT_AUTO_NEG_10BT_FD BIT(6)
919 #define PORT_AUTO_NEG_10BT BIT(5)
928 #define PORT_REMOTE_NEXT_PAGE BIT(15)
929 #define PORT_REMOTE_ACKNOWLEDGE BIT(14)
930 #define PORT_REMOTE_REMOTE_FAULT BIT(13)
931 #define PORT_REMOTE_ASYM_PAUSE BIT(11)
932 #define PORT_REMOTE_SYM_PAUSE BIT(10)
933 #define PORT_REMOTE_100BTX_FD BIT(8)
934 #define PORT_REMOTE_100BTX BIT(7)
935 #define PORT_REMOTE_10BT_FD BIT(6)
936 #define PORT_REMOTE_10BT BIT(5)
940 #define PORT_AUTO_NEG_MANUAL BIT(12)
941 #define PORT_AUTO_NEG_MASTER BIT(11)
942 #define PORT_AUTO_NEG_MASTER_PREFERRED BIT(10)
943 #define PORT_AUTO_NEG_1000BT_FD BIT(9)
944 #define PORT_AUTO_NEG_1000BT BIT(8)
948 #define PORT_MASTER_FAULT BIT(15)
949 #define PORT_LOCAL_MASTER BIT(14)
950 #define PORT_LOCAL_RX_OK BIT(13)
951 #define PORT_REMOTE_RX_OK BIT(12)
952 #define PORT_REMOTE_1000BT_FD BIT(11)
953 #define PORT_REMOTE_1000BT BIT(10)
984 #define DSP_SQI_ERR_DETECTED BIT(15)
992 #define EEE_ADV_100MBIT BIT(1)
993 #define EEE_ADV_1GBIT BIT(2)
1002 #define PORT_100BTX_FD_ABLE BIT(15)
1003 #define PORT_100BTX_ABLE BIT(14)
1004 #define PORT_10BT_FD_ABLE BIT(13)
1005 #define PORT_10BT_ABLE BIT(12)
1008 #define PORT_SGMII_AUTO_INCR BIT(23)
1011 #define PORT_SGMII_ADDR_M (BIT(21) - 1)
1014 #define PORT_SGMII_DATA_M (BIT(16) - 1)
1028 #define SR_MII_RESET BIT(15)
1029 #define SR_MII_LOOPBACK BIT(14)
1030 #define SR_MII_SPEED_100MBIT BIT(13)
1031 #define SR_MII_AUTO_NEG_ENABLE BIT(12)
1032 #define SR_MII_POWER_DOWN BIT(11)
1033 #define SR_MII_AUTO_NEG_RESTART BIT(9)
1034 #define SR_MII_FULL_DUPLEX BIT(8)
1035 #define SR_MII_SPEED_1000MBIT BIT(6)
1042 #define SR_MII_AUTO_NEG_NEXT_PAGE BIT(15)
1055 #define SR_MII_AUTO_NEG_HALF_DUPLEX BIT(6)
1056 #define SR_MII_AUTO_NEG_FULL_DUPLEX BIT(5)
1066 #define SR_MII_8_BIT BIT(8)
1067 #define SR_MII_SGMII_LINK_UP BIT(4)
1068 #define SR_MII_TX_CFG_PHY_MASTER BIT(3)
1072 #define SR_MII_AUTO_NEG_COMPLETE_INTR BIT(0)
1076 #define SR_MII_STAT_LINK_UP BIT(4)
1082 #define SR_MII_STAT_FULL_DUPLEX BIT(1)
1088 #define SR_MII_PHY_WRITE BIT(1)
1089 #define SR_MII_PHY_START_BUSY BIT(0)
1093 #define SR_MII_PHY_ADDR_M (BIT(16) - 1)
1097 #define SR_MII_PHY_DATA_M (BIT(16) - 1)
1104 #define PORT_REMOTE_LOOPBACK BIT(8)
1105 #define PORT_LED_SELECT (3 << 6)
1107 #define PORT_LED_CTRL_TEST BIT(3)
1108 #define PORT_10BT_PREAMBLE BIT(2)
1109 #define PORT_LINK_MD_10BT_ENABLE BIT(1)
1110 #define PORT_LINK_MD_PASS BIT(0)
1114 #define PORT_START_CABLE_DIAG BIT(15)
1115 #define PORT_TX_DISABLE BIT(14)
1130 #define PORT_1000_LINK_GOOD BIT(1)
1131 #define PORT_100_LINK_GOOD BIT(0)
1135 #define PORT_LINK_DETECT BIT(14)
1136 #define PORT_SIGNAL_DETECT BIT(13)
1137 #define PORT_PHY_STAT_MDI BIT(12)
1138 #define PORT_PHY_STAT_MASTER BIT(11)
1145 #define JABBER_INT BIT(7)
1146 #define RX_ERR_INT BIT(6)
1147 #define PAGE_RX_INT BIT(5)
1148 #define PARALLEL_DETECT_FAULT_INT BIT(4)
1149 #define LINK_PARTNER_ACK_INT BIT(3)
1150 #define LINK_DOWN_INT BIT(2)
1151 #define REMOTE_FAULT_INT BIT(1)
1152 #define LINK_UP_INT BIT(0)
1156 #define PORT_REG_CLK_SPEED_25_MHZ BIT(14)
1157 #define PORT_PHY_FORCE_MDI BIT(7)
1158 #define PORT_PHY_AUTO_MDIX_DISABLE BIT(6)
1161 #define PORT_PHY_PCS_LOOPBACK BIT(0)
1167 #define PORT_100BT_FIXED_LATENCY BIT(15)
1171 #define PORT_INT_PIN_HIGH BIT(14)
1172 #define PORT_ENABLE_JABBER BIT(9)
1173 #define PORT_STAT_SPEED_1000MBIT BIT(6)
1174 #define PORT_STAT_SPEED_100MBIT BIT(5)
1175 #define PORT_STAT_SPEED_10MBIT BIT(4)
1176 #define PORT_STAT_FULL_DUPLEX BIT(3)
1179 #define PORT_STAT_MASTER BIT(2)
1180 #define PORT_RESET BIT(1)
1181 #define PORT_LINK_STATUS_FAIL BIT(0)
1183 /* 3 - xMII */
1184 #define PORT_SGMII_SEL BIT(7)
1185 #define PORT_GRXC_ENABLE BIT(0)
1187 #define PORT_RMII_CLK_SEL BIT(7)
1188 #define PORT_MII_SEL_EDGE BIT(5)
1190 /* 4 - MAC */
1193 #define PORT_BROADCAST_STORM BIT(1)
1194 #define PORT_JUMBO_FRAME BIT(0)
1198 #define PORT_BACK_PRESSURE BIT(3)
1199 #define PORT_PASS_ALL BIT(0)
1203 #define PORT_100BT_EEE_DISABLE BIT(7)
1204 #define PORT_1000BT_EEE_DISABLE BIT(6)
1208 #define PORT_IN_PORT_BASED_S 6
1213 #define PORT_IN_PORT_BASED BIT(6)
1214 #define PORT_IN_PACKET_BASED BIT(5)
1215 #define PORT_IN_FLOW_CTRL BIT(4)
1222 #define PORT_COUNT_IFG BIT(1)
1223 #define PORT_COUNT_PREAMBLE BIT(0)
1239 #define PORT_RATE_LIMIT_M (BIT(7) - 1)
1241 /* 5 - MIB Counters */
1244 #define MIB_COUNTER_READ BIT(25)
1245 #define MIB_COUNTER_FLUSH_FREEZE BIT(24)
1246 #define MIB_COUNTER_INDEX_M (BIT(8) - 1)
1252 /* 6 - ACL */
1277 #define ACL_SRC BIT(1)
1278 #define ACL_EQUAL BIT(0)
1304 #define ACL_TCP_FLAG_ENABLE BIT(0)
1319 #define ACL_PRIO_MODE_S 6
1326 #define ACL_VLAN_PRIO_REPLACE BIT(2)
1341 #define ACL_CNT_M (BIT(11) - 1)
1347 #define ACL_MSEC_UNIT BIT(6)
1348 #define ACL_INTR_MODE BIT(5)
1371 #define PORT_ACL_WRITE_DONE BIT(6)
1372 #define PORT_ACL_READ_DONE BIT(5)
1373 #define PORT_ACL_WRITE BIT(4)
1378 /* 8 - Classification and Policing */
1381 #define PORT_MIRROR_RX BIT(6)
1382 #define PORT_MIRROR_TX BIT(5)
1383 #define PORT_MIRROR_SNIFFER BIT(1)
1387 #define PORT_HIGHEST_PRIO BIT(7)
1388 #define PORT_OR_PRIO BIT(6)
1389 #define PORT_MAC_PRIO_ENABLE BIT(4)
1390 #define PORT_VLAN_PRIO_ENABLE BIT(3)
1391 #define PORT_802_1P_PRIO_ENABLE BIT(2)
1392 #define PORT_DIFFSERV_PRIO_ENABLE BIT(1)
1393 #define PORT_ACL_PRIO_ENABLE BIT(0)
1397 #define PORT_USER_PRIO_CEILING BIT(7)
1398 #define PORT_DROP_NON_VLAN BIT(4)
1399 #define PORT_DROP_TAG BIT(3)
1405 #define PORT_ACL_ENABLE BIT(2)
1425 #define POLICE_DROP_ALL BIT(10)
1432 #define PORT_BASED_POLICING BIT(7)
1435 #define COLOR_MARK_ENABLE BIT(4)
1436 #define COLOR_REMAP_ENABLE BIT(3)
1437 #define POLICE_DROP_SRP BIT(2)
1438 #define POLICE_COLOR_NOT_AWARE BIT(1)
1439 #define POLICE_ENABLE BIT(0)
1447 #define POLICE_COLOR_MAP_M (BIT(POLICE_COLOR_MAP_S) - 1)
1462 #define WRED_PM_CTRL_M (BIT(11) - 1)
1477 #define WRED_RANDOM_DROP_ENABLE BIT(31)
1478 #define WRED_PMON_FLUSH BIT(30)
1479 #define WRED_DROP_GYR_DISABLE BIT(29)
1480 #define WRED_DROP_YR_DISABLE BIT(28)
1481 #define WRED_DROP_R_DISABLE BIT(27)
1482 #define WRED_DROP_ALL BIT(26)
1483 #define WRED_PMON_M (BIT(24) - 1)
1485 /* 9 - Shaping */
1489 #define MTI_PVID_REPLACE BIT(0)
1493 /* A - QM */
1505 #define PORT_QM_MIN_RESV_SPACE_M (BIT(11) - 1)
1511 #define PORT_QM_WATER_MARK_M (BIT(11) - 1)
1516 #define PORT_QM_TX_CNT_M (BIT(11) - 1)
1523 /* B - LUE */
1526 #define PORT_VLAN_LOOKUP_VID_0 BIT(7)
1527 #define PORT_INGRESS_FILTER BIT(6)
1528 #define PORT_DISCARD_NON_VID BIT(5)
1529 #define PORT_MAC_BASED_802_1X BIT(4)
1530 #define PORT_SRC_ADDR_FILTER BIT(3)
1536 /* C - PTP */
1557 #define PTP_PORT_SYNC_INT BIT(15)
1558 #define PTP_PORT_XDELAY_REQ_INT BIT(14)
1559 #define PTP_PORT_PDELAY_RESP_INT BIT(13)
1596 #define PTP_TRIG_UNIT_M (BIT(MAX_TRIG_UNIT) - 1)
1597 #define PTP_TS_UNIT_M (BIT(MAX_TIMESTAMP_UNIT) - 1)