Lines Matching refs:cdev
323 static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg) in m_can_read() argument
325 return cdev->ops->read_reg(cdev, reg); in m_can_read()
328 static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg, in m_can_write() argument
331 cdev->ops->write_reg(cdev, reg, val); in m_can_write()
335 m_can_fifo_read(struct m_can_classdev *cdev, in m_can_fifo_read() argument
338 u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE + in m_can_fifo_read()
344 return cdev->ops->read_fifo(cdev, addr_offset, val, val_count); in m_can_fifo_read()
348 m_can_fifo_write(struct m_can_classdev *cdev, in m_can_fifo_write() argument
351 u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE + in m_can_fifo_write()
357 return cdev->ops->write_fifo(cdev, addr_offset, val, val_count); in m_can_fifo_write()
360 static inline int m_can_fifo_write_no_off(struct m_can_classdev *cdev, in m_can_fifo_write_no_off() argument
363 return cdev->ops->write_fifo(cdev, fpi, &val, 1); in m_can_fifo_write_no_off()
367 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset, u32 *val) in m_can_txe_fifo_read() argument
369 u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE + in m_can_txe_fifo_read()
372 return cdev->ops->read_fifo(cdev, addr_offset, val, 1); in m_can_txe_fifo_read()
380 static inline bool m_can_tx_fifo_full(struct m_can_classdev *cdev) in m_can_tx_fifo_full() argument
382 return _m_can_tx_fifo_full(m_can_read(cdev, M_CAN_TXFQS)); in m_can_tx_fifo_full()
385 static void m_can_config_endisable(struct m_can_classdev *cdev, bool enable) in m_can_config_endisable() argument
387 u32 cccr = m_can_read(cdev, M_CAN_CCCR); in m_can_config_endisable()
397 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT); in m_can_config_endisable()
400 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE); in m_can_config_endisable()
402 m_can_write(cdev, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE)); in m_can_config_endisable()
409 while ((m_can_read(cdev, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) { in m_can_config_endisable()
411 netdev_warn(cdev->net, "Failed to init module\n"); in m_can_config_endisable()
419 static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev) in m_can_enable_all_interrupts() argument
422 m_can_write(cdev, M_CAN_ILE, ILE_EINT0); in m_can_enable_all_interrupts()
425 static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev) in m_can_disable_all_interrupts() argument
427 m_can_write(cdev, M_CAN_ILE, 0x0); in m_can_disable_all_interrupts()
433 static u32 m_can_get_timestamp(struct m_can_classdev *cdev) in m_can_get_timestamp() argument
438 tscv = m_can_read(cdev, M_CAN_TSCV); in m_can_get_timestamp()
446 struct m_can_classdev *cdev = netdev_priv(net); in m_can_clean() local
448 if (cdev->tx_skb) { in m_can_clean()
452 if (cdev->version > 30) in m_can_clean()
454 m_can_read(cdev, M_CAN_TXFQS)); in m_can_clean()
456 can_free_echo_skb(cdev->net, putidx, NULL); in m_can_clean()
457 cdev->tx_skb = NULL; in m_can_clean()
466 static void m_can_receive_skb(struct m_can_classdev *cdev, in m_can_receive_skb() argument
470 if (cdev->is_peripheral) { in m_can_receive_skb()
471 struct net_device_stats *stats = &cdev->net->stats; in m_can_receive_skb()
474 err = can_rx_offload_queue_timestamp(&cdev->offload, skb, in m_can_receive_skb()
486 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_read_fifo() local
493 err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID, &fifo_header, 2); in m_can_read_fifo()
527 err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DATA, in m_can_read_fifo()
538 m_can_receive_skb(cdev, skb, timestamp); in m_can_read_fifo()
551 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_do_rx_poll() local
560 rxfs = m_can_read(cdev, M_CAN_RXF0S); in m_can_do_rx_poll()
577 fgi = (++fgi >= cdev->mcfg[MRAM_RXF0].num ? 0 : fgi); in m_can_do_rx_poll()
581 m_can_write(cdev, M_CAN_RXF0A, ack_fgi); in m_can_do_rx_poll()
591 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_lost_msg() local
609 if (cdev->is_peripheral) in m_can_handle_lost_msg()
610 timestamp = m_can_get_timestamp(cdev); in m_can_handle_lost_msg()
612 m_can_receive_skb(cdev, skb, timestamp); in m_can_handle_lost_msg()
620 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_lec_err() local
626 cdev->can.can_stats.bus_error++; in m_can_handle_lec_err()
668 if (cdev->is_peripheral) in m_can_handle_lec_err()
669 timestamp = m_can_get_timestamp(cdev); in m_can_handle_lec_err()
671 m_can_receive_skb(cdev, skb, timestamp); in m_can_handle_lec_err()
679 struct m_can_classdev *cdev = netdev_priv(dev); in __m_can_get_berr_counter() local
682 ecr = m_can_read(cdev, M_CAN_ECR); in __m_can_get_berr_counter()
689 static int m_can_clk_start(struct m_can_classdev *cdev) in m_can_clk_start() argument
691 if (cdev->pm_clock_support == 0) in m_can_clk_start()
694 return pm_runtime_resume_and_get(cdev->dev); in m_can_clk_start()
697 static void m_can_clk_stop(struct m_can_classdev *cdev) in m_can_clk_stop() argument
699 if (cdev->pm_clock_support) in m_can_clk_stop()
700 pm_runtime_put_sync(cdev->dev); in m_can_clk_stop()
706 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_get_berr_counter() local
709 err = m_can_clk_start(cdev); in m_can_get_berr_counter()
715 m_can_clk_stop(cdev); in m_can_get_berr_counter()
723 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_state_change() local
733 cdev->can.can_stats.error_warning++; in m_can_handle_state_change()
734 cdev->can.state = CAN_STATE_ERROR_WARNING; in m_can_handle_state_change()
738 cdev->can.can_stats.error_passive++; in m_can_handle_state_change()
739 cdev->can.state = CAN_STATE_ERROR_PASSIVE; in m_can_handle_state_change()
743 cdev->can.state = CAN_STATE_BUS_OFF; in m_can_handle_state_change()
744 m_can_disable_all_interrupts(cdev); in m_can_handle_state_change()
745 cdev->can.can_stats.bus_off++; in m_can_handle_state_change()
772 ecr = m_can_read(cdev, M_CAN_ECR); in m_can_handle_state_change()
788 if (cdev->is_peripheral) in m_can_handle_state_change()
789 timestamp = m_can_get_timestamp(cdev); in m_can_handle_state_change()
791 m_can_receive_skb(cdev, skb, timestamp); in m_can_handle_state_change()
798 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_state_errors() local
801 if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) { in m_can_handle_state_errors()
807 if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) { in m_can_handle_state_errors()
813 if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) { in m_can_handle_state_errors()
849 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_protocol_error() local
861 if (cdev->version >= 31 && (irqstatus & IR_PEA)) { in m_can_handle_protocol_error()
863 cdev->can.can_stats.arbitration_lost++; in m_can_handle_protocol_error()
875 if (cdev->is_peripheral) in m_can_handle_protocol_error()
876 timestamp = m_can_get_timestamp(cdev); in m_can_handle_protocol_error()
878 m_can_receive_skb(cdev, skb, timestamp); in m_can_handle_protocol_error()
886 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_bus_errors() local
893 if (cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) { in m_can_handle_bus_errors()
909 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && in m_can_handle_bus_errors()
921 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_rx_handler() local
938 if (cdev->version <= 31 && irqstatus & IR_MRAF && in m_can_rx_handler()
939 m_can_read(cdev, M_CAN_ECR) & ECR_RP) { in m_can_rx_handler()
944 m_can_write(cdev, M_CAN_IR, IR_MRAF); in m_can_rx_handler()
951 m_can_read(cdev, M_CAN_PSR)); in m_can_rx_handler()
955 m_can_read(cdev, M_CAN_PSR)); in m_can_rx_handler()
970 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_rx_peripheral() local
979 m_can_disable_all_interrupts(cdev); in m_can_rx_peripheral()
987 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_poll() local
991 irqstatus = cdev->irqstatus | m_can_read(cdev, M_CAN_IR); in m_can_poll()
1000 m_can_enable_all_interrupts(cdev); in m_can_poll()
1010 static void m_can_tx_update_stats(struct m_can_classdev *cdev, in m_can_tx_update_stats() argument
1014 struct net_device *dev = cdev->net; in m_can_tx_update_stats()
1017 if (cdev->is_peripheral) in m_can_tx_update_stats()
1019 can_rx_offload_get_echo_skb_queue_timestamp(&cdev->offload, in m_can_tx_update_stats()
1039 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_echo_tx_event() local
1042 m_can_txefs = m_can_read(cdev, M_CAN_TXEFS); in m_can_echo_tx_event()
1053 err = m_can_txe_fifo_read(cdev, fgi, 4, &txe); in m_can_echo_tx_event()
1063 fgi = (++fgi >= cdev->mcfg[MRAM_TXE].num ? 0 : fgi); in m_can_echo_tx_event()
1066 m_can_tx_update_stats(cdev, msg_mark, timestamp); in m_can_echo_tx_event()
1070 m_can_write(cdev, M_CAN_TXEFA, FIELD_PREP(TXEFA_EFAI_MASK, in m_can_echo_tx_event()
1079 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_isr() local
1082 if (pm_runtime_suspended(cdev->dev)) in m_can_isr()
1084 ir = m_can_read(cdev, M_CAN_IR); in m_can_isr()
1089 m_can_write(cdev, M_CAN_IR, ir); in m_can_isr()
1091 if (cdev->ops->clear_interrupts) in m_can_isr()
1092 cdev->ops->clear_interrupts(cdev); in m_can_isr()
1100 cdev->irqstatus = ir; in m_can_isr()
1101 if (!cdev->is_peripheral) { in m_can_isr()
1102 m_can_disable_all_interrupts(cdev); in m_can_isr()
1103 napi_schedule(&cdev->napi); in m_can_isr()
1109 if (cdev->version == 30) { in m_can_isr()
1114 if (cdev->is_peripheral) in m_can_isr()
1115 timestamp = m_can_get_timestamp(cdev); in m_can_isr()
1116 m_can_tx_update_stats(cdev, 0, timestamp); in m_can_isr()
1126 !m_can_tx_fifo_full(cdev)) in m_can_isr()
1131 if (cdev->is_peripheral) in m_can_isr()
1132 can_rx_offload_threaded_irq_finish(&cdev->offload); in m_can_isr()
1137 m_can_disable_all_interrupts(cdev); in m_can_isr()
1191 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_set_bittiming() local
1192 const struct can_bittiming *bt = &cdev->can.bittiming; in m_can_set_bittiming()
1193 const struct can_bittiming *dbt = &cdev->can.data_bittiming; in m_can_set_bittiming()
1205 m_can_write(cdev, M_CAN_NBTP, reg_btp); in m_can_set_bittiming()
1207 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { in m_can_set_bittiming()
1229 tdco = (cdev->can.clock.freq / 1000) * in m_can_set_bittiming()
1240 m_can_write(cdev, M_CAN_TDCR, in m_can_set_bittiming()
1249 m_can_write(cdev, M_CAN_DBTP, reg_btp); in m_can_set_bittiming()
1267 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_chip_config() local
1272 err = m_can_init_ram(cdev); in m_can_chip_config()
1274 dev_err(cdev->dev, "Message RAM configuration failed\n"); in m_can_chip_config()
1283 m_can_config_endisable(cdev, true); in m_can_chip_config()
1286 m_can_write(cdev, M_CAN_RXESC, in m_can_chip_config()
1292 m_can_write(cdev, M_CAN_GFC, 0x0); in m_can_chip_config()
1294 if (cdev->version == 30) { in m_can_chip_config()
1296 m_can_write(cdev, M_CAN_TXBC, FIELD_PREP(TXBC_NDTB_MASK, 1) | in m_can_chip_config()
1297 cdev->mcfg[MRAM_TXB].off); in m_can_chip_config()
1300 m_can_write(cdev, M_CAN_TXBC, in m_can_chip_config()
1302 cdev->mcfg[MRAM_TXB].num) | in m_can_chip_config()
1303 cdev->mcfg[MRAM_TXB].off); in m_can_chip_config()
1307 m_can_write(cdev, M_CAN_TXESC, in m_can_chip_config()
1311 if (cdev->version == 30) { in m_can_chip_config()
1312 m_can_write(cdev, M_CAN_TXEFC, in m_can_chip_config()
1314 cdev->mcfg[MRAM_TXE].off); in m_can_chip_config()
1317 m_can_write(cdev, M_CAN_TXEFC, in m_can_chip_config()
1319 cdev->mcfg[MRAM_TXE].num) | in m_can_chip_config()
1320 cdev->mcfg[MRAM_TXE].off); in m_can_chip_config()
1324 m_can_write(cdev, M_CAN_RXF0C, in m_can_chip_config()
1325 FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF0].num) | in m_can_chip_config()
1326 cdev->mcfg[MRAM_RXF0].off); in m_can_chip_config()
1328 m_can_write(cdev, M_CAN_RXF1C, in m_can_chip_config()
1329 FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF1].num) | in m_can_chip_config()
1330 cdev->mcfg[MRAM_RXF1].off); in m_can_chip_config()
1332 cccr = m_can_read(cdev, M_CAN_CCCR); in m_can_chip_config()
1333 test = m_can_read(cdev, M_CAN_TEST); in m_can_chip_config()
1335 if (cdev->version == 30) { in m_can_chip_config()
1342 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) in m_can_chip_config()
1351 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO) in m_can_chip_config()
1354 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) in m_can_chip_config()
1359 if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { in m_can_chip_config()
1365 if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) in m_can_chip_config()
1369 if (cdev->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) in m_can_chip_config()
1373 m_can_write(cdev, M_CAN_CCCR, cccr); in m_can_chip_config()
1374 m_can_write(cdev, M_CAN_TEST, test); in m_can_chip_config()
1377 if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) { in m_can_chip_config()
1378 if (cdev->version == 30) in m_can_chip_config()
1383 m_can_write(cdev, M_CAN_IE, interrupts); in m_can_chip_config()
1386 m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0); in m_can_chip_config()
1394 m_can_write(cdev, M_CAN_TSCC, in m_can_chip_config()
1398 m_can_config_endisable(cdev, false); in m_can_chip_config()
1400 if (cdev->ops->init) in m_can_chip_config()
1401 cdev->ops->init(cdev); in m_can_chip_config()
1408 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_start() local
1416 cdev->can.state = CAN_STATE_ERROR_ACTIVE; in m_can_start()
1418 m_can_enable_all_interrupts(cdev); in m_can_start()
1421 dev_dbg(cdev->dev, "Start hrtimer\n"); in m_can_start()
1422 hrtimer_start(&cdev->hrtimer, ms_to_ktime(HRTIMER_POLL_INTERVAL_MS), in m_can_start()
1449 static int m_can_check_core_release(struct m_can_classdev *cdev) in m_can_check_core_release() argument
1459 crel_reg = m_can_read(cdev, M_CAN_CREL); in m_can_check_core_release()
1477 static bool m_can_niso_supported(struct m_can_classdev *cdev) in m_can_niso_supported() argument
1483 m_can_config_endisable(cdev, true); in m_can_niso_supported()
1484 cccr_reg = m_can_read(cdev, M_CAN_CCCR); in m_can_niso_supported()
1486 m_can_write(cdev, M_CAN_CCCR, cccr_reg); in m_can_niso_supported()
1489 cccr_poll = m_can_read(cdev, M_CAN_CCCR); in m_can_niso_supported()
1500 m_can_write(cdev, M_CAN_CCCR, cccr_reg); in m_can_niso_supported()
1502 m_can_config_endisable(cdev, false); in m_can_niso_supported()
1508 static int m_can_dev_setup(struct m_can_classdev *cdev) in m_can_dev_setup() argument
1510 struct net_device *dev = cdev->net; in m_can_dev_setup()
1513 m_can_version = m_can_check_core_release(cdev); in m_can_dev_setup()
1516 dev_err(cdev->dev, "Unsupported version number: %2d", in m_can_dev_setup()
1521 if (!cdev->is_peripheral) in m_can_dev_setup()
1522 netif_napi_add(dev, &cdev->napi, m_can_poll); in m_can_dev_setup()
1525 cdev->version = m_can_version; in m_can_dev_setup()
1526 cdev->can.do_set_mode = m_can_set_mode; in m_can_dev_setup()
1527 cdev->can.do_get_berr_counter = m_can_get_berr_counter; in m_can_dev_setup()
1530 cdev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | in m_can_dev_setup()
1537 switch (cdev->version) { in m_can_dev_setup()
1543 cdev->can.bittiming_const = &m_can_bittiming_const_30X; in m_can_dev_setup()
1544 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_30X; in m_can_dev_setup()
1551 cdev->can.bittiming_const = &m_can_bittiming_const_31X; in m_can_dev_setup()
1552 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X; in m_can_dev_setup()
1557 cdev->can.bittiming_const = &m_can_bittiming_const_31X; in m_can_dev_setup()
1558 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X; in m_can_dev_setup()
1560 cdev->can.ctrlmode_supported |= in m_can_dev_setup()
1561 (m_can_niso_supported(cdev) ? in m_can_dev_setup()
1565 dev_err(cdev->dev, "Unsupported version number: %2d", in m_can_dev_setup()
1566 cdev->version); in m_can_dev_setup()
1570 if (cdev->ops->init) in m_can_dev_setup()
1571 cdev->ops->init(cdev); in m_can_dev_setup()
1578 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_stop() local
1581 dev_dbg(cdev->dev, "Stop hrtimer\n"); in m_can_stop()
1582 hrtimer_cancel(&cdev->hrtimer); in m_can_stop()
1586 m_can_disable_all_interrupts(cdev); in m_can_stop()
1589 m_can_config_endisable(cdev, true); in m_can_stop()
1592 cdev->can.state = CAN_STATE_STOPPED; in m_can_stop()
1597 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_close() local
1601 if (!cdev->is_peripheral) in m_can_close()
1602 napi_disable(&cdev->napi); in m_can_close()
1605 m_can_clk_stop(cdev); in m_can_close()
1608 if (cdev->is_peripheral) { in m_can_close()
1609 cdev->tx_skb = NULL; in m_can_close()
1610 destroy_workqueue(cdev->tx_wq); in m_can_close()
1611 cdev->tx_wq = NULL; in m_can_close()
1612 can_rx_offload_disable(&cdev->offload); in m_can_close()
1617 phy_power_off(cdev->transceiver); in m_can_close()
1624 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_next_echo_skb_occupied() local
1626 unsigned int wrap = cdev->can.echo_skb_max; in m_can_next_echo_skb_occupied()
1633 return !!cdev->can.echo_skb[next_idx]; in m_can_next_echo_skb_occupied()
1636 static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev) in m_can_tx_handler() argument
1638 struct canfd_frame *cf = (struct canfd_frame *)cdev->tx_skb->data; in m_can_tx_handler()
1639 struct net_device *dev = cdev->net; in m_can_tx_handler()
1640 struct sk_buff *skb = cdev->tx_skb; in m_can_tx_handler()
1647 cdev->tx_skb = NULL; in m_can_tx_handler()
1661 if (cdev->version == 30) { in m_can_tx_handler()
1667 err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, &fifo_header, 2); in m_can_tx_handler()
1671 err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_DATA, in m_can_tx_handler()
1676 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { in m_can_tx_handler()
1677 cccr = m_can_read(cdev, M_CAN_CCCR); in m_can_tx_handler()
1689 m_can_write(cdev, M_CAN_CCCR, cccr); in m_can_tx_handler()
1691 m_can_write(cdev, M_CAN_TXBTIE, 0x1); in m_can_tx_handler()
1695 m_can_write(cdev, M_CAN_TXBAR, 0x1); in m_can_tx_handler()
1700 txfqs = m_can_read(cdev, M_CAN_TXFQS); in m_can_tx_handler()
1709 if (cdev->is_peripheral) { in m_can_tx_handler()
1737 err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, &fifo_header, 2); in m_can_tx_handler()
1741 err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DATA, in m_can_tx_handler()
1752 m_can_write(cdev, M_CAN_TXBAR, (1 << putidx)); in m_can_tx_handler()
1755 if (m_can_tx_fifo_full(cdev) || in m_can_tx_handler()
1764 m_can_disable_all_interrupts(cdev); in m_can_tx_handler()
1770 struct m_can_classdev *cdev = container_of(ws, struct m_can_classdev, in m_can_tx_work_queue() local
1773 m_can_tx_handler(cdev); in m_can_tx_work_queue()
1779 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_start_xmit() local
1784 if (cdev->is_peripheral) { in m_can_start_xmit()
1785 if (cdev->tx_skb) { in m_can_start_xmit()
1790 if (cdev->can.state == CAN_STATE_BUS_OFF) { in m_can_start_xmit()
1798 cdev->tx_skb = skb; in m_can_start_xmit()
1799 netif_stop_queue(cdev->net); in m_can_start_xmit()
1800 queue_work(cdev->tx_wq, &cdev->tx_work); in m_can_start_xmit()
1803 cdev->tx_skb = skb; in m_can_start_xmit()
1804 return m_can_tx_handler(cdev); in m_can_start_xmit()
1812 struct m_can_classdev *cdev = container_of(timer, struct in hrtimer_callback() local
1815 m_can_isr(0, cdev->net); in hrtimer_callback()
1824 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_open() local
1827 err = phy_power_on(cdev->transceiver); in m_can_open()
1831 err = m_can_clk_start(cdev); in m_can_open()
1842 if (cdev->is_peripheral) in m_can_open()
1843 can_rx_offload_enable(&cdev->offload); in m_can_open()
1846 if (cdev->is_peripheral) { in m_can_open()
1847 cdev->tx_skb = NULL; in m_can_open()
1848 cdev->tx_wq = alloc_workqueue("mcan_wq", in m_can_open()
1850 if (!cdev->tx_wq) { in m_can_open()
1855 INIT_WORK(&cdev->tx_work, m_can_tx_work_queue); in m_can_open()
1875 if (!cdev->is_peripheral) in m_can_open()
1876 napi_enable(&cdev->napi); in m_can_open()
1883 if (cdev->is_peripheral) in m_can_open()
1884 destroy_workqueue(cdev->tx_wq); in m_can_open()
1886 if (cdev->is_peripheral) in m_can_open()
1887 can_rx_offload_disable(&cdev->offload); in m_can_open()
1890 m_can_clk_stop(cdev); in m_can_open()
1892 phy_power_off(cdev->transceiver); in m_can_open()
1916 int m_can_check_mram_cfg(struct m_can_classdev *cdev, u32 mram_max_size) in m_can_check_mram_cfg() argument
1920 total_size = cdev->mcfg[MRAM_TXB].off - cdev->mcfg[MRAM_SIDF].off + in m_can_check_mram_cfg()
1921 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; in m_can_check_mram_cfg()
1923 dev_err(cdev->dev, "Total size of mram config(%u) exceeds mram(%u)\n", in m_can_check_mram_cfg()
1932 static void m_can_of_parse_mram(struct m_can_classdev *cdev, in m_can_of_parse_mram() argument
1935 cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0]; in m_can_of_parse_mram()
1936 cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1]; in m_can_of_parse_mram()
1937 cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off + in m_can_of_parse_mram()
1938 cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE; in m_can_of_parse_mram()
1939 cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2]; in m_can_of_parse_mram()
1940 cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off + in m_can_of_parse_mram()
1941 cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE; in m_can_of_parse_mram()
1942 cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] & in m_can_of_parse_mram()
1944 cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off + in m_can_of_parse_mram()
1945 cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE; in m_can_of_parse_mram()
1946 cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] & in m_can_of_parse_mram()
1948 cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off + in m_can_of_parse_mram()
1949 cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE; in m_can_of_parse_mram()
1950 cdev->mcfg[MRAM_RXB].num = mram_config_vals[5]; in m_can_of_parse_mram()
1951 cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off + in m_can_of_parse_mram()
1952 cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE; in m_can_of_parse_mram()
1953 cdev->mcfg[MRAM_TXE].num = mram_config_vals[6]; in m_can_of_parse_mram()
1954 cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off + in m_can_of_parse_mram()
1955 cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE; in m_can_of_parse_mram()
1956 cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] & in m_can_of_parse_mram()
1959 dev_dbg(cdev->dev, in m_can_of_parse_mram()
1961 cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num, in m_can_of_parse_mram()
1962 cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num, in m_can_of_parse_mram()
1963 cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num, in m_can_of_parse_mram()
1964 cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num, in m_can_of_parse_mram()
1965 cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num, in m_can_of_parse_mram()
1966 cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num, in m_can_of_parse_mram()
1967 cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num); in m_can_of_parse_mram()
1970 int m_can_init_ram(struct m_can_classdev *cdev) in m_can_init_ram() argument
1978 start = cdev->mcfg[MRAM_SIDF].off; in m_can_init_ram()
1979 end = cdev->mcfg[MRAM_TXB].off + in m_can_init_ram()
1980 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; in m_can_init_ram()
1983 err = m_can_fifo_write_no_off(cdev, i, 0x0); in m_can_init_ram()
1992 int m_can_class_get_clocks(struct m_can_classdev *cdev) in m_can_class_get_clocks() argument
1996 cdev->hclk = devm_clk_get(cdev->dev, "hclk"); in m_can_class_get_clocks()
1997 cdev->cclk = devm_clk_get(cdev->dev, "cclk"); in m_can_class_get_clocks()
1999 if (IS_ERR(cdev->hclk) || IS_ERR(cdev->cclk)) { in m_can_class_get_clocks()
2000 dev_err(cdev->dev, "no clock found\n"); in m_can_class_get_clocks()
2055 int m_can_class_register(struct m_can_classdev *cdev) in m_can_class_register() argument
2059 if (cdev->pm_clock_support) { in m_can_class_register()
2060 ret = m_can_clk_start(cdev); in m_can_class_register()
2065 if (cdev->is_peripheral) { in m_can_class_register()
2066 ret = can_rx_offload_add_manual(cdev->net, &cdev->offload, in m_can_class_register()
2072 if (!cdev->net->irq) in m_can_class_register()
2073 cdev->hrtimer.function = &hrtimer_callback; in m_can_class_register()
2075 ret = m_can_dev_setup(cdev); in m_can_class_register()
2079 ret = register_m_can_dev(cdev->net); in m_can_class_register()
2081 dev_err(cdev->dev, "registering %s failed (err=%d)\n", in m_can_class_register()
2082 cdev->net->name, ret); in m_can_class_register()
2086 of_can_transceiver(cdev->net); in m_can_class_register()
2088 dev_info(cdev->dev, "%s device registered (irq=%d, version=%d)\n", in m_can_class_register()
2089 KBUILD_MODNAME, cdev->net->irq, cdev->version); in m_can_class_register()
2094 m_can_clk_stop(cdev); in m_can_class_register()
2099 if (cdev->is_peripheral) in m_can_class_register()
2100 can_rx_offload_del(&cdev->offload); in m_can_class_register()
2102 m_can_clk_stop(cdev); in m_can_class_register()
2108 void m_can_class_unregister(struct m_can_classdev *cdev) in m_can_class_unregister() argument
2110 if (cdev->is_peripheral) in m_can_class_unregister()
2111 can_rx_offload_del(&cdev->offload); in m_can_class_unregister()
2112 unregister_candev(cdev->net); in m_can_class_unregister()
2118 struct m_can_classdev *cdev = dev_get_drvdata(dev); in m_can_class_suspend() local
2119 struct net_device *ndev = cdev->net; in m_can_class_suspend()
2125 m_can_clk_stop(cdev); in m_can_class_suspend()
2130 cdev->can.state = CAN_STATE_SLEEPING; in m_can_class_suspend()
2138 struct m_can_classdev *cdev = dev_get_drvdata(dev); in m_can_class_resume() local
2139 struct net_device *ndev = cdev->net; in m_can_class_resume()
2143 cdev->can.state = CAN_STATE_ERROR_ACTIVE; in m_can_class_resume()
2148 ret = m_can_clk_start(cdev); in m_can_class_resume()
2153 m_can_clk_stop(cdev); in m_can_class_resume()