325 static inline void grcan_write_reg(u32 __iomem *reg, u32 val)  in grcan_write_reg()  function
335 static inline void grcan_write_reg(u32 __iomem *reg, u32 val)  in grcan_write_reg()  function
343 	grcan_write_reg(reg, grcan_read_reg(reg) & ~mask);  in grcan_clear_bits()
348 	grcan_write_reg(reg, grcan_read_reg(reg) | mask);  in grcan_set_bits()
360 	grcan_write_reg(reg, (old & ~mask) | (value & mask));  in grcan_write_bits()
470 	grcan_write_reg(&regs->conf, config);  in grcan_reset()
476 	grcan_write_reg(&regs->rxmask, 0);  in grcan_reset()
485 	grcan_write_reg(&regs->imr, GRCAN_IRQ_NONE);  in grcan_stop_hardware()
559 		grcan_write_reg(&regs->txrd, txrd);  in grcan_lost_one_shot_frame()
773 	grcan_write_reg(&regs->picr, sources);  in grcan_interrupt()
841 		grcan_write_reg(&regs->txaddr, txaddr);  in grcan_running_reset()
842 		grcan_write_reg(&regs->txsize, txsize);  in grcan_running_reset()
843 		grcan_write_reg(&regs->txwr, txwr);  in grcan_running_reset()
844 		grcan_write_reg(&regs->txrd, txrd);  in grcan_running_reset()
847 		grcan_write_reg(&regs->rxaddr, rxaddr);  in grcan_running_reset()
848 		grcan_write_reg(&regs->rxsize, rxsize);  in grcan_running_reset()
849 		grcan_write_reg(&regs->rxwr, rxwr);  in grcan_running_reset()
850 		grcan_write_reg(&regs->rxrd, rxrd);  in grcan_running_reset()
853 		grcan_write_reg(&regs->imr, imr);  in grcan_running_reset()
855 		grcan_write_reg(&regs->txctrl, GRCAN_TXCTRL_ENABLE  in grcan_running_reset()
858 		grcan_write_reg(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);  in grcan_running_reset()
859 		grcan_write_reg(&regs->ctrl, GRCAN_CTRL_ENABLE);  in grcan_running_reset()
983 	grcan_write_reg(&regs->txaddr, priv->dma.tx.handle);  in grcan_start()
984 	grcan_write_reg(&regs->txsize, priv->dma.tx.size);  in grcan_start()
987 	grcan_write_reg(&regs->rxaddr, priv->dma.rx.handle);  in grcan_start()
988 	grcan_write_reg(&regs->rxsize, priv->dma.rx.size);  in grcan_start()
993 	grcan_write_reg(&regs->imr, GRCAN_IRQ_DEFAULT);  in grcan_start()
1008 	grcan_write_reg(&regs->txctrl, txctrl);  in grcan_start()
1009 	grcan_write_reg(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);  in grcan_start()
1010 	grcan_write_reg(&regs->ctrl, GRCAN_CTRL_ENABLE);  in grcan_start()
1223 		grcan_write_reg(&regs->rxrd, rd);  in grcan_receive()
1444 	grcan_write_reg(&regs->txwr,  in grcan_start_xmit()
1635 	grcan_write_reg(&regs->ctrl, GRCAN_CTRL_RESET);  in grcan_setup_netdev()