138 	void __iomem *conf_regs;  member
218 	       nfc->conf_regs + PL35X_SMC_DIRECT_CMD);  in pl35x_smc_update_regs()
226 	writel(bw, nfc->conf_regs + PL35X_SMC_OPMODE);  in pl35x_smc_set_buswidth()
235 	       nfc->conf_regs + PL35X_SMC_MEMC_CFG_CLR);  in pl35x_smc_clear_irq()
243 	ret = readl_poll_timeout(nfc->conf_regs + PL35X_SMC_MEMC_STATUS, reg,  in pl35x_smc_wait_for_irq()
261 	ret = readl_poll_timeout(nfc->conf_regs + PL35X_SMC_ECC_STATUS, reg,  in pl35x_smc_wait_for_ecc_done()
278 	ecc_cfg = readl(nfc->conf_regs + PL35X_SMC_ECC_CFG);  in pl35x_smc_set_ecc_mode()
281 	writel(ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG);  in pl35x_smc_set_ecc_mode()
322 	writel(plnand->timings, nfc->conf_regs + PL35X_SMC_CYCLES);  in pl35x_nand_select_target()
326 	writel(plnand->ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG);  in pl35x_nand_select_target()
456 		ecc_value = readl(nfc->conf_regs + PL35X_SMC_ECC_VALUE(chunk));  in pl35x_nand_read_eccbytes()
479 		ecc_value = readl(nfc->conf_regs + PL35X_SMC_ECC_VALUE(chunk));  in pl35x_nand_recover_data_hwecc()
890 	plnand->ecc_cfg = readl(nfc->conf_regs + PL35X_SMC_ECC_CFG);  in pl35x_smc_set_ecc_pg_size()
893 	writel(plnand->ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG);  in pl35x_smc_set_ecc_pg_size()
1008 	       nfc->conf_regs + PL35X_SMC_MEMC_CFG_CLR);  in pl35x_nand_reset_state()
1028 	       nfc->conf_regs + PL35X_SMC_ECC_CMD1);  in pl35x_nand_reset_state()
1033 	       nfc->conf_regs + PL35X_SMC_ECC_CMD2);  in pl35x_nand_reset_state()
1152 	nfc->conf_regs = devm_ioremap_resource(&smc_amba->dev, &smc_amba->res);  in pl35x_nand_probe()
1153 	if (IS_ERR(nfc->conf_regs))  in pl35x_nand_probe()
1154 		return PTR_ERR(nfc->conf_regs);  in pl35x_nand_probe()