1 // SPDX-License-Identifier: GPL-2.0
3  * ARM PL35X NAND flash controller driver
31 #define PL35X_NANDC_DRIVER_NAME "pl35x-nand-controller"
58 /* SMC ECC status register (RO) */
61 /* SMC ECC configuration register */
68 /* SMC ECC command 1 register */
74 /* SMC ECC command 2 register */
80 /* SMC ECC value registers (RO) */
86 /* NAND AXI interface */
126  * struct pl35x_nandc - NAND flash controller driver structure
129  * @io_regs: NAND data registers for data phase
130  * @controller: Core NAND controller structure
131  * @chip: NAND chip information structure
132  * @selected_chip: NAND chip currently selected by the controller
134  * @ecc_buf: Temporary buffer to extract ECC bytes
162 	if (section >= chip->ecc.steps)  in pl35x_ecc_ooblayout16_ecc()
163 		return -ERANGE;  in pl35x_ecc_ooblayout16_ecc()
165 	oobregion->offset = (section * chip->ecc.bytes);  in pl35x_ecc_ooblayout16_ecc()
166 	oobregion->length = chip->ecc.bytes;  in pl35x_ecc_ooblayout16_ecc()
176 	if (section >= chip->ecc.steps)  in pl35x_ecc_ooblayout16_free()
177 		return -ERANGE;  in pl35x_ecc_ooblayout16_free()
179 	oobregion->offset = (section * chip->ecc.bytes) + 8;  in pl35x_ecc_ooblayout16_free()
180 	oobregion->length = 8;  in pl35x_ecc_ooblayout16_free()
186 	.ecc = pl35x_ecc_ooblayout16_ecc,
218 	       nfc->conf_regs + PL35X_SMC_DIRECT_CMD);  in pl35x_smc_update_regs()
224 		return -EINVAL;  in pl35x_smc_set_buswidth()
226 	writel(bw, nfc->conf_regs + PL35X_SMC_OPMODE);  in pl35x_smc_set_buswidth()
235 	       nfc->conf_regs + PL35X_SMC_MEMC_CFG_CLR);  in pl35x_smc_clear_irq()
243 	ret = readl_poll_timeout(nfc->conf_regs + PL35X_SMC_MEMC_STATUS, reg,  in pl35x_smc_wait_for_irq()
247 		dev_err(nfc->dev,  in pl35x_smc_wait_for_irq()
248 			"Timeout polling on NAND controller interrupt (0x%x)\n",  in pl35x_smc_wait_for_irq()
261 	ret = readl_poll_timeout(nfc->conf_regs + PL35X_SMC_ECC_STATUS, reg,  in pl35x_smc_wait_for_ecc_done()
265 		dev_err(nfc->dev,  in pl35x_smc_wait_for_ecc_done()
266 			"Timeout polling on ECC controller interrupt\n");  in pl35x_smc_wait_for_ecc_done()
278 	ecc_cfg = readl(nfc->conf_regs + PL35X_SMC_ECC_CFG);  in pl35x_smc_set_ecc_mode()
281 	writel(ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG);  in pl35x_smc_set_ecc_mode()
285 		plnand->ecc_cfg = ecc_cfg;  in pl35x_smc_set_ecc_mode()
297 	struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);  in pl35x_smc_force_byte_access()
300 	if (!(chip->options & NAND_BUSWIDTH_16))  in pl35x_smc_force_byte_access()
309 		dev_err(nfc->dev, "Error in Buswidth\n");  in pl35x_smc_force_byte_access()
315 	struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);  in pl35x_nand_select_target()
318 	if (chip == nfc->selected_chip)  in pl35x_nand_select_target()
322 	writel(plnand->timings, nfc->conf_regs + PL35X_SMC_CYCLES);  in pl35x_nand_select_target()
325 	/* Configure the ECC engine */  in pl35x_nand_select_target()
326 	writel(plnand->ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG);  in pl35x_nand_select_target()
328 	nfc->selected_chip = chip;  in pl35x_nand_select_target()
335 	struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);  in pl35x_nand_read_data_op()
351 		buf32[i] = readl(nfc->io_regs + data_phase_addr);  in pl35x_nand_read_data_op()
356 		buf8[i] = readb(nfc->io_regs + PL35X_SMC_DATA_PHASE);  in pl35x_nand_read_data_op()
367 	struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);  in pl35x_nand_write_data_op()
383 		writel(buf32[i], nfc->io_regs + data_phase_addr);  in pl35x_nand_write_data_op()
388 		writeb(buf8[i], nfc->io_regs + PL35X_SMC_DATA_PHASE);  in pl35x_nand_write_data_op()
431 	/* One error in the ECC data; no action needed */  in pl35x_nand_correct_data()
435 	return -EBADMSG;  in pl35x_nand_correct_data()
444 	for (ecc_byte = 0; ecc_byte < chip->ecc.bytes; ecc_byte++)  in pl35x_nand_ecc_reg_to_array()
454 	for (chunk = 0; chunk < chip->ecc.steps;  in pl35x_nand_read_eccbytes()
455 	     chunk++, read_ecc += chip->ecc.bytes) {  in pl35x_nand_read_eccbytes()
456 		ecc_value = readl(nfc->conf_regs + PL35X_SMC_ECC_VALUE(chunk));  in pl35x_nand_read_eccbytes()
458 			return -EINVAL;  in pl35x_nand_read_eccbytes()
476 	for (chunk = 0; chunk < chip->ecc.steps;  in pl35x_nand_recover_data_hwecc()
477 	     chunk++, data += chip->ecc.size, read_ecc += chip->ecc.bytes) {  in pl35x_nand_recover_data_hwecc()
478 		/* Read ECC value for each chunk */  in pl35x_nand_recover_data_hwecc()
479 		ecc_value = readl(nfc->conf_regs + PL35X_SMC_ECC_VALUE(chunk));  in pl35x_nand_recover_data_hwecc()
482 			return -EINVAL;  in pl35x_nand_recover_data_hwecc()
485 			mtd->ecc_stats.failed++;  in pl35x_nand_recover_data_hwecc()
492 			mtd->ecc_stats.failed++;  in pl35x_nand_recover_data_hwecc()
494 			mtd->ecc_stats.corrected += stats;  in pl35x_nand_recover_data_hwecc()
506 	struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);  in pl35x_nand_write_page_hwecc()
509 	unsigned int first_row = (mtd->writesize <= 512) ? 1 : 2;  in pl35x_nand_write_page_hwecc()
510 	unsigned int nrows = plnand->addr_cycles;  in pl35x_nand_write_page_hwecc()
521 		   PL35X_SMC_CMD_PHASE_NADDRS(plnand->addr_cycles) |  in pl35x_nand_write_page_hwecc()
530 			addr2 |= PL35X_SMC_CMD_PHASE_ADDR(row - 4, addr);  in pl35x_nand_write_page_hwecc()
534 	writel(addr1, nfc->io_regs + cmd_addr);  in pl35x_nand_write_page_hwecc()
535 	if (plnand->addr_cycles > 4)  in pl35x_nand_write_page_hwecc()
536 		writel(addr2, nfc->io_regs + cmd_addr);  in pl35x_nand_write_page_hwecc()
538 	/* Write the data with the engine enabled */  in pl35x_nand_write_page_hwecc()
539 	pl35x_nand_write_data_op(chip, buf, mtd->writesize, false,  in pl35x_nand_write_page_hwecc()
545 	/* Copy the HW calculated ECC bytes in the OOB buffer */  in pl35x_nand_write_page_hwecc()
546 	ret = pl35x_nand_read_eccbytes(nfc, chip, nfc->ecc_buf);  in pl35x_nand_write_page_hwecc()
551 		memset(chip->oob_poi, 0xFF, mtd->oobsize);  in pl35x_nand_write_page_hwecc()
553 	ret = mtd_ooblayout_set_eccbytes(mtd, nfc->ecc_buf, chip->oob_poi,  in pl35x_nand_write_page_hwecc()
554 					 0, chip->ecc.total);  in pl35x_nand_write_page_hwecc()
558 	/* Write the spare area with ECC bytes */  in pl35x_nand_write_page_hwecc()
559 	pl35x_nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false, 0,  in pl35x_nand_write_page_hwecc()
573 		ret = -EIO;  in pl35x_nand_write_page_hwecc()
583  * generated ECC values and read ECC values from spare area.
586  * last data access to tell the ECC engine not to expect any further data.
588  * and doing a last 4-byte transfer with the additional bit set. The last block
589  * should be aligned with the end of an ECC block. Because of this limitation,
597 	struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);  in pl35x_nand_read_page_hwecc()
600 	unsigned int first_row = (mtd->writesize <= 512) ? 1 : 2;  in pl35x_nand_read_page_hwecc()
601 	unsigned int nrows = plnand->addr_cycles;  in pl35x_nand_read_page_hwecc()
611 		   PL35X_SMC_CMD_PHASE_NADDRS(plnand->addr_cycles) |  in pl35x_nand_read_page_hwecc()
622 			addr2 |= PL35X_SMC_CMD_PHASE_ADDR(row - 4, addr);  in pl35x_nand_read_page_hwecc()
626 	writel(addr1, nfc->io_regs + cmd_addr);  in pl35x_nand_read_page_hwecc()
627 	if (plnand->addr_cycles > 4)  in pl35x_nand_read_page_hwecc()
628 		writel(addr2, nfc->io_regs + cmd_addr);  in pl35x_nand_read_page_hwecc()
630 	/* Wait the data to be available in the NAND cache */  in pl35x_nand_read_page_hwecc()
631 	ndelay(PSEC_TO_NSEC(sdr->tRR_min));  in pl35x_nand_read_page_hwecc()
636 	/* Retrieve the raw data with the engine enabled */  in pl35x_nand_read_page_hwecc()
637 	pl35x_nand_read_data_op(chip, buf, mtd->writesize, false,  in pl35x_nand_read_page_hwecc()
643 	/* Retrieve the stored ECC bytes */  in pl35x_nand_read_page_hwecc()
644 	pl35x_nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false,  in pl35x_nand_read_page_hwecc()
646 	ret = mtd_ooblayout_get_eccbytes(mtd, nfc->ecc_buf, chip->oob_poi, 0,  in pl35x_nand_read_page_hwecc()
647 					 chip->ecc.total);  in pl35x_nand_read_page_hwecc()
654 	return pl35x_nand_recover_data_hwecc(nfc, chip, buf, nfc->ecc_buf);  in pl35x_nand_read_page_hwecc()
665 	struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);  in pl35x_nand_exec_op()
670 	int last_instr_type = -1;  in pl35x_nand_exec_op()
675 	for (op_id = 0; op_id < subop->ninstrs; op_id++) {  in pl35x_nand_exec_op()
676 		instr = &subop->instrs[op_id];  in pl35x_nand_exec_op()
678 		switch (instr->type) {  in pl35x_nand_exec_op()
681 				cmd0 = PL35X_SMC_CMD_PHASE_CMD0(instr->ctx.cmd.opcode);  in pl35x_nand_exec_op()
683 				cmd1 = PL35X_SMC_CMD_PHASE_CMD1(instr->ctx.cmd.opcode);  in pl35x_nand_exec_op()
693 			addrs = &instr->ctx.addr.addrs[offset];  in pl35x_nand_exec_op()
700 					addr2 |= PL35X_SMC_CMD_PHASE_ADDR(i - 4, addrs[i]);  in pl35x_nand_exec_op()
711 			rdy_tim_ms = instr->ctx.waitrdy.timeout_ms;  in pl35x_nand_exec_op()
712 			rdy_del_ns = instr->delay_ns;  in pl35x_nand_exec_op()
716 		last_instr_type = instr->type;  in pl35x_nand_exec_op()
722 	writel(addr1, nfc->io_regs + cmd_addr);  in pl35x_nand_exec_op()
724 		writel(addr2, nfc->io_regs + cmd_addr);  in pl35x_nand_exec_op()
727 	if (data_instr && data_instr->type == NAND_OP_DATA_OUT_INSTR) {  in pl35x_nand_exec_op()
732 		pl35x_nand_write_data_op(chip, data_instr->ctx.data.buf.out,  in pl35x_nand_exec_op()
733 					 len, data_instr->ctx.data.force_8bit,  in pl35x_nand_exec_op()
744 	if (data_instr && data_instr->type == NAND_OP_DATA_IN_INSTR)  in pl35x_nand_exec_op()
745 		pl35x_nand_read_data_op(chip, data_instr->ctx.data.buf.in,  in pl35x_nand_exec_op()
746 					len, data_instr->ctx.data.force_8bit,  in pl35x_nand_exec_op()
778 		pl35x_nand_select_target(chip, op->cs);  in pl35x_nfc_exec_op()
787 	struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);  in pl35x_nfc_setup_interface()
798 	mclk = of_clk_get_by_name(nfc->dev->parent->of_node, "memclk");  in pl35x_nfc_setup_interface()
800 		dev_err(nfc->dev, "Failed to retrieve SMC memclk\n");  in pl35x_nfc_setup_interface()
805 	 * SDR timings are given in pico-seconds while NFC timings must be  in pl35x_nfc_setup_interface()
806 	 * expressed in NAND controller clock cycles. We use the TO_CYCLE()  in pl35x_nfc_setup_interface()
815 	val = TO_CYCLES(sdr->tRC_min, period_ns);  in pl35x_nfc_setup_interface()
816 	if (sdr->tRC_min <= 20000)  in pl35x_nfc_setup_interface()
821 		return -EINVAL;  in pl35x_nfc_setup_interface()
823 	val = TO_CYCLES(sdr->tWC_min, period_ns);  in pl35x_nfc_setup_interface()
826 		return -EINVAL;  in pl35x_nfc_setup_interface()
834 	val = TO_CYCLES(sdr->tWP_min, period_ns);  in pl35x_nfc_setup_interface()
837 		return -EINVAL;  in pl35x_nfc_setup_interface()
839 	val = TO_CYCLES(sdr->tCLR_min, period_ns);  in pl35x_nfc_setup_interface()
842 		return -EINVAL;  in pl35x_nfc_setup_interface()
844 	val = TO_CYCLES(sdr->tAR_min, period_ns);  in pl35x_nfc_setup_interface()
847 		return -EINVAL;  in pl35x_nfc_setup_interface()
849 	val = TO_CYCLES(sdr->tRR_min, period_ns);  in pl35x_nfc_setup_interface()
852 		return -EINVAL;  in pl35x_nfc_setup_interface()
857 	plnand->timings = PL35X_SMC_NAND_TRC_CYCLES(tmgs.t_rc) |  in pl35x_nfc_setup_interface()
890 	plnand->ecc_cfg = readl(nfc->conf_regs + PL35X_SMC_ECC_CFG);  in pl35x_smc_set_ecc_pg_size()
891 	plnand->ecc_cfg &= ~PL35X_SMC_ECC_CFG_PGSIZE_MASK;  in pl35x_smc_set_ecc_pg_size()
892 	plnand->ecc_cfg |= sz;  in pl35x_smc_set_ecc_pg_size()
893 	writel(plnand->ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG);  in pl35x_smc_set_ecc_pg_size()
902 	if (mtd->writesize < SZ_512 || mtd->writesize > SZ_2K) {  in pl35x_nand_init_hw_ecc_controller()
903 		dev_err(nfc->dev,  in pl35x_nand_init_hw_ecc_controller()
904 			"The hardware ECC engine is limited to pages up to 2kiB\n");  in pl35x_nand_init_hw_ecc_controller()
905 		return -EOPNOTSUPP;  in pl35x_nand_init_hw_ecc_controller()
908 	chip->ecc.strength = 1;  in pl35x_nand_init_hw_ecc_controller()
909 	chip->ecc.bytes = 3;  in pl35x_nand_init_hw_ecc_controller()
910 	chip->ecc.size = SZ_512;  in pl35x_nand_init_hw_ecc_controller()
911 	chip->ecc.steps = mtd->writesize / chip->ecc.size;  in pl35x_nand_init_hw_ecc_controller()
912 	chip->ecc.read_page = pl35x_nand_read_page_hwecc;  in pl35x_nand_init_hw_ecc_controller()
913 	chip->ecc.write_page = pl35x_nand_write_page_hwecc;  in pl35x_nand_init_hw_ecc_controller()
914 	chip->ecc.write_page_raw = nand_monolithic_write_page_raw;  in pl35x_nand_init_hw_ecc_controller()
915 	pl35x_smc_set_ecc_pg_size(nfc, chip, mtd->writesize);  in pl35x_nand_init_hw_ecc_controller()
917 	nfc->ecc_buf = devm_kmalloc(nfc->dev, chip->ecc.bytes * chip->ecc.steps,  in pl35x_nand_init_hw_ecc_controller()
919 	if (!nfc->ecc_buf)  in pl35x_nand_init_hw_ecc_controller()
920 		return -ENOMEM;  in pl35x_nand_init_hw_ecc_controller()
922 	switch (mtd->oobsize) {  in pl35x_nand_init_hw_ecc_controller()
926 		chip->bbt_options |= NAND_BBT_NO_OOB_BBM;  in pl35x_nand_init_hw_ecc_controller()
932 		dev_err(nfc->dev, "Unsupported OOB size\n");  in pl35x_nand_init_hw_ecc_controller()
933 		return -EOPNOTSUPP;  in pl35x_nand_init_hw_ecc_controller()
942 		nanddev_get_ecc_requirements(&chip->base);  in pl35x_nand_attach_chip()
943 	struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller);  in pl35x_nand_attach_chip()
948 	if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_NONE &&  in pl35x_nand_attach_chip()
949 	    (!chip->ecc.size || !chip->ecc.strength)) {  in pl35x_nand_attach_chip()
950 		if (requirements->step_size && requirements->strength) {  in pl35x_nand_attach_chip()
951 			chip->ecc.size = requirements->step_size;  in pl35x_nand_attach_chip()
952 			chip->ecc.strength = requirements->strength;  in pl35x_nand_attach_chip()
954 			dev_info(nfc->dev,  in pl35x_nand_attach_chip()
955 				 "No minimum ECC strength, using 1b/512B\n");  in pl35x_nand_attach_chip()
956 			chip->ecc.size = 512;  in pl35x_nand_attach_chip()
957 			chip->ecc.strength = 1;  in pl35x_nand_attach_chip()
961 	if (mtd->writesize <= SZ_512)  in pl35x_nand_attach_chip()
962 		plnand->addr_cycles = 1;  in pl35x_nand_attach_chip()
964 		plnand->addr_cycles = 2;  in pl35x_nand_attach_chip()
966 	if (chip->options & NAND_ROW_ADDR_3)  in pl35x_nand_attach_chip()
967 		plnand->addr_cycles += 3;  in pl35x_nand_attach_chip()
969 		plnand->addr_cycles += 2;  in pl35x_nand_attach_chip()
971 	switch (chip->ecc.engine_type) {  in pl35x_nand_attach_chip()
974 		chip->bbt_td = &bbt_main_descr;  in pl35x_nand_attach_chip()
975 		chip->bbt_md = &bbt_mirror_descr;  in pl35x_nand_attach_chip()
986 		dev_err(nfc->dev, "Unsupported ECC mode: %d\n",  in pl35x_nand_attach_chip()
987 			chip->ecc.engine_type);  in pl35x_nand_attach_chip()
988 		return -EINVAL;  in pl35x_nand_attach_chip()
1008 	       nfc->conf_regs + PL35X_SMC_MEMC_CFG_CLR);  in pl35x_nand_reset_state()
1010 	/* Set default bus width to 8-bit */  in pl35x_nand_reset_state()
1015 	/* Ensure the ECC controller is bypassed by default */  in pl35x_nand_reset_state()
1021 	 * Configure the commands that the ECC block uses to detect the  in pl35x_nand_reset_state()
1028 	       nfc->conf_regs + PL35X_SMC_ECC_CMD1);  in pl35x_nand_reset_state()
1033 	       nfc->conf_regs + PL35X_SMC_ECC_CMD2);  in pl35x_nand_reset_state()
1046 	plnand = devm_kzalloc(nfc->dev, sizeof(*plnand), GFP_KERNEL);  in pl35x_nand_chip_init()
1048 		return -ENOMEM;  in pl35x_nand_chip_init()
1055 		dev_err(nfc->dev, "Wrong CS %d\n", cs);  in pl35x_nand_chip_init()
1056 		return -EINVAL;  in pl35x_nand_chip_init()
1059 	if (test_and_set_bit(cs, &nfc->assigned_cs)) {  in pl35x_nand_chip_init()
1060 		dev_err(nfc->dev, "Already assigned CS %d\n", cs);  in pl35x_nand_chip_init()
1061 		return -EINVAL;  in pl35x_nand_chip_init()
1064 	plnand->cs = cs;  in pl35x_nand_chip_init()
1066 	chip = &plnand->chip;  in pl35x_nand_chip_init()
1067 	chip->options = NAND_BUSWIDTH_AUTO | NAND_USES_DMA | NAND_NO_SUBPAGE_WRITE;  in pl35x_nand_chip_init()
1068 	chip->bbt_options = NAND_BBT_USE_FLASH;  in pl35x_nand_chip_init()
1069 	chip->controller = &nfc->controller;  in pl35x_nand_chip_init()
1071 	mtd->dev.parent = nfc->dev;  in pl35x_nand_chip_init()
1073 	if (!mtd->name) {  in pl35x_nand_chip_init()
1074 		mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,  in pl35x_nand_chip_init()
1076 		if (!mtd->name) {  in pl35x_nand_chip_init()
1077 			dev_err(nfc->dev, "Failed to allocate mtd->name\n");  in pl35x_nand_chip_init()
1078 			return -ENOMEM;  in pl35x_nand_chip_init()
1092 	list_add_tail(&plnand->node, &nfc->chips);  in pl35x_nand_chip_init()
1103 	list_for_each_entry_safe(plnand, tmp, &nfc->chips, node) {  in pl35x_nand_chips_cleanup()
1104 		chip = &plnand->chip;  in pl35x_nand_chips_cleanup()
1108 		list_del(&plnand->node);  in pl35x_nand_chips_cleanup()
1114 	struct device_node *np = nfc->dev->of_node, *nand_np;  in pl35x_nand_chips_init()
1119 		dev_err(nfc->dev, "Incorrect number of NAND chips (%d)\n",  in pl35x_nand_chips_init()
1121 		return -EINVAL;  in pl35x_nand_chips_init()
1138 	struct device *smc_dev = pdev->dev.parent;  in pl35x_nand_probe()
1143 	nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);  in pl35x_nand_probe()
1145 		return -ENOMEM;  in pl35x_nand_probe()
1147 	nfc->dev = &pdev->dev;  in pl35x_nand_probe()
1148 	nand_controller_init(&nfc->controller);  in pl35x_nand_probe()
1149 	nfc->controller.ops = &pl35x_nandc_ops;  in pl35x_nand_probe()
1150 	INIT_LIST_HEAD(&nfc->chips);  in pl35x_nand_probe()
1152 	nfc->conf_regs = devm_ioremap_resource(&smc_amba->dev, &smc_amba->res);  in pl35x_nand_probe()
1153 	if (IS_ERR(nfc->conf_regs))  in pl35x_nand_probe()
1154 		return PTR_ERR(nfc->conf_regs);  in pl35x_nand_probe()
1156 	nfc->io_regs = devm_platform_ioremap_resource(pdev, 0);  in pl35x_nand_probe()
1157 	if (IS_ERR(nfc->io_regs))  in pl35x_nand_probe()
1158 		return PTR_ERR(nfc->io_regs);  in pl35x_nand_probe()
1181 	{ .compatible = "arm,pl353-nand-r2p1" },
1198 MODULE_DESCRIPTION("ARM PL35X NAND controller driver");