Lines Matching +full:nand +full:- +full:ecc +full:- +full:engine
1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
13 * The main visible difference is that NFCv1 only has Hamming ECC
14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
21 * or 4) and each chunk will have its own ECC "digest" of 6B at the
23 * bytes (also called "spare" bytes in the driver). This engine
28 * +-------------------------------------------------------------+
29 * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes |
30 * +-------------------------------------------------------------+
32 * When using the BCH engine, there are N identical (data + free OOB +
33 * ECC) sections and potentially an extra one to deal with
34 * configurations where the chosen (data + free OOB + ECC) sizes do
35 * not align with the page (data + OOB) size. ECC bytes are always
36 * 30B per ECC chunk. Here is the page layout used by the controller
39 * +-----------------------------------------
40 * | Data 1 | Free OOB bytes 1 | ECC 1 | ...
41 * +-----------------------------------------
43 * -------------------------------------------
44 * ... | Data N | Free OOB bytes N | ECC N |
45 * -------------------------------------------
47 * --------------------------------------------+
48 * Last Data | Last Free OOB bytes | Last ECC |
49 * --------------------------------------------+
52 * first, then all free OOB bytes and finally all ECC bytes. With BCH,
53 * ECC bytes are 30B long and are padded with 0xFF to align on 32
58 * - It can only read 2k at a time. To overcome this limitation, the
61 * - The ECC strength in BCH mode cannot be tuned. It is fixed 16
62 * bits. What can be tuned is the ECC block size as long as it
64 * chip ECC requirements. For instance, using 2kiB ECC chunks
66 * - The controller will always treat data bytes, free OOB bytes
67 * and ECC bytes in that order, no matter what the real layout is
71 * - Because of these weird layouts, the Bad Block Markers can be
90 #include <linux/dma-mapping.h>
91 #include <linux/dma/pxa-dma.h>
92 #include <linux/platform_data/mtd-nand-pxa3xx.h>
112 /* System control registers/bits to enable the NAND controller on some SoCs */
124 /* NAND controller data flash control register */
143 /* NAND interface timing parameter 0 register */
157 /* NAND interface timing parameter 1 register */
166 /* NAND controller status register */
173 #define NDSR_CMDD(cs) BIT(8 - cs)
177 /* NAND ECC control register */
181 /* NAND controller data buffer register */
184 /* NAND controller command buffer 0 register */
197 /* NAND controller command buffer 1 register */
202 /* NAND controller command buffer 2 register */
207 /* NAND controller command buffer 3 register */
212 /* NAND controller command buffer 0 register 'type' and 'xtype' fields */
232 * struct marvell_hw_ecc_layout - layout of Marvell ECC
234 * Marvell ECC engine works differently than the others, in order to limit the
236 * per subpage, and depending on a the desired strength needed by the NAND chip,
237 * a particular layout mixing data/spare/ecc is defined, with a possible last
241 * @chunk: Desired ECC chunk size on which the layout applies
242 * @strength: Desired ECC strength (per chunk size bytes) on which the
245 * @full_chunk_cnt: Number of full-sized chunks, which is the number of
250 * @ecc_bytes: Number of ecc bytes per chunk
253 * @last_ecc_bytes: Number of ecc bytes in the last chunk
286 /* Layouts explained in AN-379_Marvell_SoC_NFC_ECC */
306 * struct marvell_nand_chip_sel - CS line description
308 * The Nand Flash Controller has up to 4 CE and 2 RB pins. The CE selection
328 * struct marvell_nand_chip - stores NAND chip device related information
330 * @chip: Base NAND chip structure
331 * @node: Used to store NAND chips into a list
332 * @layout: NAND layout when using hardware ECC
333 * @ndcr: Controller register value for this NAND chip
334 * @ndtr0: Timing registers 0 value for this NAND chip
335 * @ndtr1: Timing registers 1 value for this NAND chip
338 * @nsels: Number of CS lines required by the NAND chip
360 *nand) in to_nand_sel()
362 return &nand->sels[nand->selected_die]; in to_nand_sel()
366 * struct marvell_nfc_caps - NAND controller capabilities for distinction
372 * system controller (ie. to enable the NAND controller)
392 * struct marvell_nfc - stores Marvell NAND controller information
396 * @regs: NAND controller registers
399 * @complete: Completion object to wait for NAND controller events
401 * @chips: List containing all the NAND chips attached to
402 * this NAND controller
404 * @caps: NAND controller capabilities for each compatible string
407 * @dma_buf: 32-bit aligned buffer for DMA transfers (NFCv1 only)
433 * struct marvell_nfc_timings - NAND controller timings expressed in NAND
465 * TO_CYCLES() - Derives a duration in numbers of clock cycles.
467 * @ps: Duration in pico-seconds
468 * @period_ns: Clock period in nano-seconds
470 * Convert the duration in nano-seconds, then divide by the period and
478 * struct marvell_nfc_op - filled during the parsing of the ->exec_op()
524 reg = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_disable_int()
525 writel_relaxed(reg | int_mask, nfc->regs + NDCR); in marvell_nfc_disable_int()
533 reg = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_enable_int()
534 writel_relaxed(reg & ~int_mask, nfc->regs + NDCR); in marvell_nfc_enable_int()
541 reg = readl_relaxed(nfc->regs + NDSR); in marvell_nfc_clear_int()
542 writel_relaxed(int_mask, nfc->regs + NDSR); in marvell_nfc_clear_int()
550 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_force_byte_access()
554 * Callers of this function do not verify if the NAND is using a 16-bit in marvell_nfc_force_byte_access()
555 * an 8-bit bus for normal operations, so we need to take care of that in marvell_nfc_force_byte_access()
556 * here by leaving the configuration unchanged if the NAND does not have in marvell_nfc_force_byte_access()
559 if (!(chip->options & NAND_BUSWIDTH_16)) in marvell_nfc_force_byte_access()
562 ndcr = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_force_byte_access()
569 writel_relaxed(ndcr, nfc->regs + NDCR); in marvell_nfc_force_byte_access()
574 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_wait_ndrun()
582 ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val, in marvell_nfc_wait_ndrun()
586 dev_err(nfc->dev, "Timeout on NAND controller run mode\n"); in marvell_nfc_wait_ndrun()
587 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, in marvell_nfc_wait_ndrun()
588 nfc->regs + NDCR); in marvell_nfc_wait_ndrun()
598 * - call marvell_nfc_prepare_cmd()
599 * -> activate the ND_RUN bit that will kind of 'start a job'
600 * -> wait the signal indicating the NFC is waiting for a command
601 * - send the command (cmd and address cycles)
602 * - enventually send or receive the data
603 * - call marvell_nfc_end_cmd() with the corresponding flag
604 * -> wait the flag to be triggered or cancel the job with a timeout
607 * specialized functions responsible for executing the actual NAND
612 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_prepare_cmd()
619 dev_err(nfc->dev, "Last operation did not succeed\n"); in marvell_nfc_prepare_cmd()
623 ndcr = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_prepare_cmd()
624 writel_relaxed(readl(nfc->regs + NDSR), nfc->regs + NDSR); in marvell_nfc_prepare_cmd()
627 writel_relaxed(ndcr | NDCR_ND_RUN, nfc->regs + NDCR); in marvell_nfc_prepare_cmd()
628 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, in marvell_nfc_prepare_cmd()
632 dev_err(nfc->dev, "Timeout on WRCMDRE\n"); in marvell_nfc_prepare_cmd()
633 return -ETIMEDOUT; in marvell_nfc_prepare_cmd()
637 writel_relaxed(NDSR_WRCMDREQ, nfc->regs + NDSR); in marvell_nfc_prepare_cmd()
646 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_send_cmd()
648 dev_dbg(nfc->dev, "\nNDCR: 0x%08x\n" in marvell_nfc_send_cmd()
650 (u32)readl_relaxed(nfc->regs + NDCR), nfc_op->ndcb[0], in marvell_nfc_send_cmd()
651 nfc_op->ndcb[1], nfc_op->ndcb[2], nfc_op->ndcb[3]); in marvell_nfc_send_cmd()
653 writel_relaxed(to_nand_sel(marvell_nand)->ndcb0_csel | nfc_op->ndcb[0], in marvell_nfc_send_cmd()
654 nfc->regs + NDCB0); in marvell_nfc_send_cmd()
655 writel_relaxed(nfc_op->ndcb[1], nfc->regs + NDCB0); in marvell_nfc_send_cmd()
656 writel(nfc_op->ndcb[2], nfc->regs + NDCB0); in marvell_nfc_send_cmd()
662 if (nfc_op->ndcb[0] & NDCB0_LEN_OVRD || in marvell_nfc_send_cmd()
663 NDCB0_ADDR_GET_NUM_CYC(nfc_op->ndcb[0]) >= 6) { in marvell_nfc_send_cmd()
664 if (!WARN_ON_ONCE(!nfc->caps->is_nfcv2)) in marvell_nfc_send_cmd()
665 writel(nfc_op->ndcb[3], nfc->regs + NDCB0); in marvell_nfc_send_cmd()
672 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_end_cmd()
676 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, in marvell_nfc_end_cmd()
681 dev_err(nfc->dev, "Timeout on %s (NDSR: 0x%08x)\n", in marvell_nfc_end_cmd()
683 if (nfc->dma_chan) in marvell_nfc_end_cmd()
684 dmaengine_terminate_all(nfc->dma_chan); in marvell_nfc_end_cmd()
692 if (nfc->use_dma && (readl_relaxed(nfc->regs + NDCR) & NDCR_DMA_EN)) in marvell_nfc_end_cmd()
695 writel_relaxed(flag, nfc->regs + NDSR); in marvell_nfc_end_cmd()
703 int cs_flag = NDSR_CMDD(to_nand_sel(marvell_nand)->ndcb0_csel); in marvell_nfc_wait_cmdd()
716 st = readl_relaxed(nfc->regs + NDSR); in marvell_nfc_poll_status()
726 return -ETIMEDOUT; in marvell_nfc_poll_status()
731 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_wait_op()
740 if (mtd->oops_panic_write) { in marvell_nfc_wait_op()
745 init_completion(&nfc->complete); in marvell_nfc_wait_op()
748 ret = wait_for_completion_timeout(&nfc->complete, in marvell_nfc_wait_op()
759 dev_err(nfc->dev, "Timeout waiting for RB signal\n"); in marvell_nfc_wait_op()
760 return -ETIMEDOUT; in marvell_nfc_wait_op()
770 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_select_target()
777 ndcr_generic = readl_relaxed(nfc->regs + NDCR) & in marvell_nfc_select_target()
779 writel_relaxed(ndcr_generic | marvell_nand->ndcr, nfc->regs + NDCR); in marvell_nfc_select_target()
784 if (chip == nfc->selected_chip && die_nr == marvell_nand->selected_die) in marvell_nfc_select_target()
787 writel_relaxed(marvell_nand->ndtr0, nfc->regs + NDTR0); in marvell_nfc_select_target()
788 writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1); in marvell_nfc_select_target()
790 nfc->selected_chip = chip; in marvell_nfc_select_target()
791 marvell_nand->selected_die = die_nr; in marvell_nfc_select_target()
797 u32 st = readl_relaxed(nfc->regs + NDSR); in marvell_nfc_isr()
798 u32 ien = (~readl_relaxed(nfc->regs + NDCR)) & NDCR_ALL_INT; in marvell_nfc_isr()
813 complete(&nfc->complete); in marvell_nfc_isr()
818 /* HW ECC related functions */
821 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_enable_hw_ecc()
822 u32 ndcr = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_enable_hw_ecc()
825 writel_relaxed(ndcr | NDCR_ECC_EN, nfc->regs + NDCR); in marvell_nfc_enable_hw_ecc()
831 if (chip->ecc.algo == NAND_ECC_ALGO_BCH) in marvell_nfc_enable_hw_ecc()
832 writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL); in marvell_nfc_enable_hw_ecc()
838 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_disable_hw_ecc()
839 u32 ndcr = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_disable_hw_ecc()
842 writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR); in marvell_nfc_disable_hw_ecc()
843 if (chip->ecc.algo == NAND_ECC_ALGO_BCH) in marvell_nfc_disable_hw_ecc()
844 writel_relaxed(0, nfc->regs + NDECCCTRL); in marvell_nfc_disable_hw_ecc()
853 reg = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_enable_dma()
854 writel_relaxed(reg | NDCR_DMA_EN, nfc->regs + NDCR); in marvell_nfc_enable_dma()
861 reg = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_disable_dma()
862 writel_relaxed(reg & ~NDCR_DMA_EN, nfc->regs + NDCR); in marvell_nfc_disable_dma()
878 sg_init_one(&sg, nfc->dma_buf, dma_len); in marvell_nfc_xfer_data_dma()
879 ret = dma_map_sg(nfc->dma_chan->device->dev, &sg, 1, direction); in marvell_nfc_xfer_data_dma()
881 dev_err(nfc->dev, "Could not map DMA S/G list\n"); in marvell_nfc_xfer_data_dma()
882 return -ENXIO; in marvell_nfc_xfer_data_dma()
885 tx = dmaengine_prep_slave_sg(nfc->dma_chan, &sg, 1, in marvell_nfc_xfer_data_dma()
890 dev_err(nfc->dev, "Could not prepare DMA S/G list\n"); in marvell_nfc_xfer_data_dma()
891 dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction); in marvell_nfc_xfer_data_dma()
892 return -ENXIO; in marvell_nfc_xfer_data_dma()
899 return -EIO; in marvell_nfc_xfer_data_dma()
901 dma_async_issue_pending(nfc->dma_chan); in marvell_nfc_xfer_data_dma()
902 ret = marvell_nfc_wait_cmdd(nfc->selected_chip); in marvell_nfc_xfer_data_dma()
903 dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction); in marvell_nfc_xfer_data_dma()
906 dev_err(nfc->dev, "Timeout waiting for DMA (status: %d)\n", in marvell_nfc_xfer_data_dma()
907 dmaengine_tx_status(nfc->dma_chan, cookie, NULL)); in marvell_nfc_xfer_data_dma()
908 dmaengine_terminate_all(nfc->dma_chan); in marvell_nfc_xfer_data_dma()
909 return -ETIMEDOUT; in marvell_nfc_xfer_data_dma()
923 ioread32_rep(nfc->regs + NDDB, in + i, FIFO_REP(FIFO_DEPTH)); in marvell_nfc_xfer_data_in_pio()
928 ioread32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH)); in marvell_nfc_xfer_data_in_pio()
943 iowrite32_rep(nfc->regs + NDDB, out + i, FIFO_REP(FIFO_DEPTH)); in marvell_nfc_xfer_data_out_pio()
949 iowrite32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH)); in marvell_nfc_xfer_data_out_pio()
958 u8 *ecc, int ecc_len, in marvell_nfc_check_empty_chunk() argument
967 * check if the entire page (with ECC bytes) is actually blank or not. in marvell_nfc_check_empty_chunk()
973 if (!ecc) in marvell_nfc_check_empty_chunk()
976 bf = nand_check_erased_ecc_chunk(data, data_len, ecc, ecc_len, in marvell_nfc_check_empty_chunk()
977 spare, spare_len, chip->ecc.strength); in marvell_nfc_check_empty_chunk()
979 mtd->ecc_stats.failed++; in marvell_nfc_check_empty_chunk()
984 mtd->ecc_stats.corrected += bf; in marvell_nfc_check_empty_chunk()
989 * Check if a chunk is correct or not according to the hardware ECC engine.
990 * mtd->ecc_stats.corrected is updated, as well as max_bitflips, however
991 * mtd->ecc_stats.failure is not, the function will instead return a non-zero
999 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_check_bitflips()
1003 ndsr = readl_relaxed(nfc->regs + NDSR); in marvell_nfc_hw_ecc_check_bitflips()
1007 writel_relaxed(ndsr, nfc->regs + NDSR); in marvell_nfc_hw_ecc_check_bitflips()
1010 * Do not increment ->ecc_stats.failed now, instead, return a in marvell_nfc_hw_ecc_check_bitflips()
1011 * non-zero value to indicate that this chunk was apparently in marvell_nfc_hw_ecc_check_bitflips()
1013 * the chunk (with ECC bytes) is not declared empty, the calling in marvell_nfc_hw_ecc_check_bitflips()
1016 return -EBADMSG; in marvell_nfc_hw_ecc_check_bitflips()
1021 writel_relaxed(ndsr, nfc->regs + NDSR); in marvell_nfc_hw_ecc_check_bitflips()
1023 if (chip->ecc.algo == NAND_ECC_ALGO_BCH) in marvell_nfc_hw_ecc_check_bitflips()
1030 mtd->ecc_stats.corrected += bf; in marvell_nfc_hw_ecc_check_bitflips()
1042 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_hmg_do_read_page()
1043 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_hmg_do_read_page()
1046 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | in marvell_nfc_hw_ecc_hmg_do_read_page()
1053 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); in marvell_nfc_hw_ecc_hmg_do_read_page()
1057 if (nfc->caps->is_nfcv2) in marvell_nfc_hw_ecc_hmg_do_read_page()
1072 * documentation, spare bytes are protected by the ECC engine, and must in marvell_nfc_hw_ecc_hmg_do_read_page()
1076 if (nfc->use_dma) { in marvell_nfc_hw_ecc_hmg_do_read_page()
1078 lt->data_bytes + oob_bytes); in marvell_nfc_hw_ecc_hmg_do_read_page()
1079 memcpy(data_buf, nfc->dma_buf, lt->data_bytes); in marvell_nfc_hw_ecc_hmg_do_read_page()
1080 memcpy(oob_buf, nfc->dma_buf + lt->data_bytes, oob_bytes); in marvell_nfc_hw_ecc_hmg_do_read_page()
1082 marvell_nfc_xfer_data_in_pio(nfc, data_buf, lt->data_bytes); in marvell_nfc_hw_ecc_hmg_do_read_page()
1093 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_read_page_raw()
1094 return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_read_page_raw()
1101 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_hmg_read_page()
1102 unsigned int full_sz = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; in marvell_nfc_hw_ecc_hmg_read_page()
1106 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_read_page()
1108 marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, false, in marvell_nfc_hw_ecc_hmg_read_page()
1117 * When ECC failures are detected, check if the full page has been in marvell_nfc_hw_ecc_hmg_read_page()
1122 return -ENOMEM; in marvell_nfc_hw_ecc_hmg_read_page()
1125 lt->data_bytes, true, page); in marvell_nfc_hw_ecc_hmg_read_page()
1134 * Spare area in Hamming layouts is not protected by the ECC engine (even if
1135 * it appears before the ECC bytes when reading), the ->read_oob_raw() function
1136 * also stands for ->read_oob().
1142 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_read_oob_raw()
1143 return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_read_oob_raw()
1156 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_hmg_do_write_page()
1157 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_hmg_do_write_page()
1160 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | in marvell_nfc_hw_ecc_hmg_do_write_page()
1167 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); in marvell_nfc_hw_ecc_hmg_do_write_page()
1172 if (nfc->caps->is_nfcv2) in marvell_nfc_hw_ecc_hmg_do_write_page()
1186 if (nfc->use_dma) { in marvell_nfc_hw_ecc_hmg_do_write_page()
1187 memcpy(nfc->dma_buf, data_buf, lt->data_bytes); in marvell_nfc_hw_ecc_hmg_do_write_page()
1188 memcpy(nfc->dma_buf + lt->data_bytes, oob_buf, oob_bytes); in marvell_nfc_hw_ecc_hmg_do_write_page()
1189 marvell_nfc_xfer_data_dma(nfc, DMA_TO_DEVICE, lt->data_bytes + in marvell_nfc_hw_ecc_hmg_do_write_page()
1190 lt->ecc_bytes + lt->spare_bytes); in marvell_nfc_hw_ecc_hmg_do_write_page()
1192 marvell_nfc_xfer_data_out_pio(nfc, data_buf, lt->data_bytes); in marvell_nfc_hw_ecc_hmg_do_write_page()
1201 PSEC_TO_MSEC(sdr->tPROG_max)); in marvell_nfc_hw_ecc_hmg_do_write_page()
1211 return -EIO; in marvell_nfc_hw_ecc_hmg_do_write_page()
1220 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_write_page_raw()
1221 return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_write_page_raw()
1231 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_write_page()
1233 ret = marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_write_page()
1241 * Spare area in Hamming layouts is not protected by the ECC engine (even if
1242 * it appears before the ECC bytes when reading), the ->write_oob_raw() function
1243 * also stands for ->write_oob().
1251 memset(buf, 0xFF, mtd->writesize); in marvell_nfc_hw_ecc_hmg_write_oob_raw()
1253 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_write_oob_raw()
1254 return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_write_oob_raw()
1263 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_read_page_raw()
1264 u8 *oob = chip->oob_poi; in marvell_nfc_hw_ecc_bch_read_page_raw()
1265 int chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1266 int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + in marvell_nfc_hw_ecc_bch_read_page_raw()
1267 lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1268 int data_len = lt->data_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1269 int spare_len = lt->spare_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1270 int ecc_len = lt->ecc_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1273 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_bch_read_page_raw()
1276 memset(chip->oob_poi, 0xFF, mtd->oobsize); in marvell_nfc_hw_ecc_bch_read_page_raw()
1280 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_read_page_raw()
1282 if (chunk >= lt->full_chunk_cnt) { in marvell_nfc_hw_ecc_bch_read_page_raw()
1283 data_len = lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1284 spare_len = lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1285 ecc_len = lt->last_ecc_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1290 buf + (lt->data_bytes * chunk), in marvell_nfc_hw_ecc_bch_read_page_raw()
1294 nand_read_data_op(chip, oob + (lt->spare_bytes * chunk), in marvell_nfc_hw_ecc_bch_read_page_raw()
1297 /* Read ECC bytes */ in marvell_nfc_hw_ecc_bch_read_page_raw()
1299 (ALIGN(lt->ecc_bytes, 32) * chunk), in marvell_nfc_hw_ecc_bch_read_page_raw()
1312 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_bch_read_chunk()
1313 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_read_chunk()
1317 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | in marvell_nfc_hw_ecc_bch_read_chunk()
1339 else if (chunk < lt->nchunks - 1) in marvell_nfc_hw_ecc_bch_read_chunk()
1351 * Drain the FIFO, 8 32-bit reads at a time, and skip in marvell_nfc_hw_ecc_bch_read_chunk()
1378 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_read_page()
1379 int data_len = lt->data_bytes, spare_len = lt->spare_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1380 u8 *data = buf, *spare = chip->oob_poi; in marvell_nfc_hw_ecc_bch_read_page()
1385 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_bch_read_page()
1393 memset(chip->oob_poi, 0xFF, mtd->oobsize); in marvell_nfc_hw_ecc_bch_read_page()
1397 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_read_page()
1399 if (chunk >= lt->full_chunk_cnt) { in marvell_nfc_hw_ecc_bch_read_page()
1400 data_len = lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1401 spare_len = lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1421 * Please note that dumping the ECC bytes during a normal read with OOB in marvell_nfc_hw_ecc_bch_read_page()
1422 * area would add a significant overhead as ECC bytes are "consumed" by in marvell_nfc_hw_ecc_bch_read_page()
1423 * the controller in normal mode and must be re-read in raw mode. To in marvell_nfc_hw_ecc_bch_read_page()
1425 * user should re-read the page in raw mode if ECC bytes are required. in marvell_nfc_hw_ecc_bch_read_page()
1429 * In case there is any subpage read error, we usually re-read only ECC in marvell_nfc_hw_ecc_bch_read_page()
1431 * it is normal that the ECC check failed and we just ignore the error. in marvell_nfc_hw_ecc_bch_read_page()
1436 * this strange behavior, the whole page is re-read in raw mode, not in marvell_nfc_hw_ecc_bch_read_page()
1437 * only the ECC bytes. in marvell_nfc_hw_ecc_bch_read_page()
1439 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_read_page()
1448 data_off_in_page = chunk * (lt->data_bytes + lt->spare_bytes + in marvell_nfc_hw_ecc_bch_read_page()
1449 lt->ecc_bytes); in marvell_nfc_hw_ecc_bch_read_page()
1451 (chunk < lt->full_chunk_cnt ? lt->data_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1452 lt->last_data_bytes); in marvell_nfc_hw_ecc_bch_read_page()
1454 (chunk < lt->full_chunk_cnt ? lt->spare_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1455 lt->last_spare_bytes); in marvell_nfc_hw_ecc_bch_read_page()
1457 data_off = chunk * lt->data_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1458 spare_off = chunk * lt->spare_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1459 ecc_off = (lt->full_chunk_cnt * lt->spare_bytes) + in marvell_nfc_hw_ecc_bch_read_page()
1460 lt->last_spare_bytes + in marvell_nfc_hw_ecc_bch_read_page()
1461 (chunk * (lt->ecc_bytes + 2)); in marvell_nfc_hw_ecc_bch_read_page()
1463 data_len = chunk < lt->full_chunk_cnt ? lt->data_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1464 lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1465 spare_len = chunk < lt->full_chunk_cnt ? lt->spare_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1466 lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1467 ecc_len = chunk < lt->full_chunk_cnt ? lt->ecc_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1468 lt->last_ecc_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1471 * Only re-read the ECC bytes, unless we are using the 2k/8b in marvell_nfc_hw_ecc_bch_read_page()
1472 * layout which is buggy in the sense that the ECC engine will in marvell_nfc_hw_ecc_bch_read_page()
1474 * case, re-read the entire page. in marvell_nfc_hw_ecc_bch_read_page()
1476 if (lt->writesize == 2048 && lt->strength == 8) { in marvell_nfc_hw_ecc_bch_read_page()
1481 chip->oob_poi + spare_off, spare_len, in marvell_nfc_hw_ecc_bch_read_page()
1486 chip->oob_poi + ecc_off, ecc_len, in marvell_nfc_hw_ecc_bch_read_page()
1489 /* Check the entire chunk (data + spare + ecc) for emptyness */ in marvell_nfc_hw_ecc_bch_read_page()
1491 chip->oob_poi + spare_off, spare_len, in marvell_nfc_hw_ecc_bch_read_page()
1492 chip->oob_poi + ecc_off, ecc_len, in marvell_nfc_hw_ecc_bch_read_page()
1503 return chip->ecc.read_page_raw(chip, buf, true, page); in marvell_nfc_hw_ecc_bch_read_oob_raw()
1510 return chip->ecc.read_page(chip, buf, true, page); in marvell_nfc_hw_ecc_bch_read_oob()
1518 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_write_page_raw()
1519 int full_chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1520 int data_len = lt->data_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1521 int spare_len = lt->spare_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1522 int ecc_len = lt->ecc_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1524 int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + in marvell_nfc_hw_ecc_bch_write_page_raw()
1525 lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1528 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_bch_write_page_raw()
1532 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_write_page_raw()
1533 if (chunk >= lt->full_chunk_cnt) { in marvell_nfc_hw_ecc_bch_write_page_raw()
1534 data_len = lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1535 spare_len = lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1536 ecc_len = lt->last_ecc_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1544 nand_write_data_op(chip, buf + (chunk * lt->data_bytes), in marvell_nfc_hw_ecc_bch_write_page_raw()
1552 nand_write_data_op(chip, chip->oob_poi + spare_offset, in marvell_nfc_hw_ecc_bch_write_page_raw()
1555 /* Write the ECC bytes */ in marvell_nfc_hw_ecc_bch_write_page_raw()
1557 nand_write_data_op(chip, chip->oob_poi + ecc_offset, in marvell_nfc_hw_ecc_bch_write_page_raw()
1574 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_bch_write_chunk()
1575 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_write_chunk()
1592 if (lt->nchunks == 1) in marvell_nfc_hw_ecc_bch_write_chunk()
1598 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | in marvell_nfc_hw_ecc_bch_write_chunk()
1602 } else if (chunk < lt->nchunks - 1) { in marvell_nfc_hw_ecc_bch_write_chunk()
1609 if (chunk == lt->nchunks - 1) in marvell_nfc_hw_ecc_bch_write_chunk()
1623 iowrite32_rep(nfc->regs + NDDB, data, FIFO_REP(data_len)); in marvell_nfc_hw_ecc_bch_write_chunk()
1624 iowrite32_rep(nfc->regs + NDDB, spare, FIFO_REP(spare_len)); in marvell_nfc_hw_ecc_bch_write_chunk()
1636 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_write_page()
1638 const u8 *spare = chip->oob_poi; in marvell_nfc_hw_ecc_bch_write_page()
1639 int data_len = lt->data_bytes; in marvell_nfc_hw_ecc_bch_write_page()
1640 int spare_len = lt->spare_bytes; in marvell_nfc_hw_ecc_bch_write_page()
1644 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_bch_write_page()
1648 memset(chip->oob_poi, 0xFF, mtd->oobsize); in marvell_nfc_hw_ecc_bch_write_page()
1652 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_write_page()
1653 if (chunk >= lt->full_chunk_cnt) { in marvell_nfc_hw_ecc_bch_write_page()
1654 data_len = lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_write_page()
1655 spare_len = lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_write_page()
1664 * Waiting only for CMDD or PAGED is not enough, ECC are in marvell_nfc_hw_ecc_bch_write_page()
1672 ret = marvell_nfc_wait_op(chip, PSEC_TO_MSEC(sdr->tPROG_max)); in marvell_nfc_hw_ecc_bch_write_page()
1685 return -EIO; in marvell_nfc_hw_ecc_bch_write_page()
1696 memset(buf, 0xFF, mtd->writesize); in marvell_nfc_hw_ecc_bch_write_oob_raw()
1698 return chip->ecc.write_page_raw(chip, buf, true, page); in marvell_nfc_hw_ecc_bch_write_oob_raw()
1706 memset(buf, 0xFF, mtd->writesize); in marvell_nfc_hw_ecc_bch_write_oob()
1708 return chip->ecc.write_page(chip, buf, true, page); in marvell_nfc_hw_ecc_bch_write_oob()
1711 /* NAND framework ->exec_op() hooks and related helpers */
1717 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_parse_instructions()
1725 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in marvell_nfc_parse_instructions()
1730 instr = &subop->instrs[op_id]; in marvell_nfc_parse_instructions()
1732 switch (instr->type) { in marvell_nfc_parse_instructions()
1735 nfc_op->ndcb[0] |= in marvell_nfc_parse_instructions()
1736 NDCB0_CMD1(instr->ctx.cmd.opcode); in marvell_nfc_parse_instructions()
1738 nfc_op->ndcb[0] |= in marvell_nfc_parse_instructions()
1739 NDCB0_CMD2(instr->ctx.cmd.opcode) | in marvell_nfc_parse_instructions()
1742 nfc_op->cle_ale_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1749 addrs = &instr->ctx.addr.addrs[offset]; in marvell_nfc_parse_instructions()
1751 nfc_op->ndcb[0] |= NDCB0_ADDR_CYC(naddrs); in marvell_nfc_parse_instructions()
1754 nfc_op->ndcb[1] |= addrs[i] << (8 * i); in marvell_nfc_parse_instructions()
1757 nfc_op->ndcb[2] |= NDCB2_ADDR5_CYC(addrs[4]); in marvell_nfc_parse_instructions()
1759 nfc_op->ndcb[3] |= NDCB3_ADDR6_CYC(addrs[5]); in marvell_nfc_parse_instructions()
1761 nfc_op->ndcb[3] |= NDCB3_ADDR7_CYC(addrs[6]); in marvell_nfc_parse_instructions()
1763 nfc_op->cle_ale_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1767 nfc_op->data_instr = instr; in marvell_nfc_parse_instructions()
1768 nfc_op->data_instr_idx = op_id; in marvell_nfc_parse_instructions()
1769 nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ); in marvell_nfc_parse_instructions()
1770 if (nfc->caps->is_nfcv2) { in marvell_nfc_parse_instructions()
1771 nfc_op->ndcb[0] |= in marvell_nfc_parse_instructions()
1775 nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH); in marvell_nfc_parse_instructions()
1777 nfc_op->data_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1781 nfc_op->data_instr = instr; in marvell_nfc_parse_instructions()
1782 nfc_op->data_instr_idx = op_id; in marvell_nfc_parse_instructions()
1783 nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE); in marvell_nfc_parse_instructions()
1784 if (nfc->caps->is_nfcv2) { in marvell_nfc_parse_instructions()
1785 nfc_op->ndcb[0] |= in marvell_nfc_parse_instructions()
1789 nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH); in marvell_nfc_parse_instructions()
1791 nfc_op->data_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1795 nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms; in marvell_nfc_parse_instructions()
1796 nfc_op->rdy_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1806 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_xfer_data_pio()
1807 const struct nand_op_instr *instr = nfc_op->data_instr; in marvell_nfc_xfer_data_pio()
1808 unsigned int op_id = nfc_op->data_instr_idx; in marvell_nfc_xfer_data_pio()
1811 bool reading = (instr->type == NAND_OP_DATA_IN_INSTR); in marvell_nfc_xfer_data_pio()
1814 if (instr->ctx.data.force_8bit) in marvell_nfc_xfer_data_pio()
1818 u8 *in = instr->ctx.data.buf.in + offset; in marvell_nfc_xfer_data_pio()
1822 const u8 *out = instr->ctx.data.buf.out + offset; in marvell_nfc_xfer_data_pio()
1827 if (instr->ctx.data.force_8bit) in marvell_nfc_xfer_data_pio()
1841 reading = (nfc_op.data_instr->type == NAND_OP_DATA_IN_INSTR); in marvell_nfc_monolithic_access_exec()
1888 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_monolithic_access_exec()
1890 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, in marvell_nfc_monolithic_access_exec()
1891 nfc->regs + NDCR); in marvell_nfc_monolithic_access_exec()
1912 switch (subop->instrs[0].type) { in marvell_nfc_naked_access_exec()
1959 if (subop->instrs[0].type == NAND_OP_DATA_OUT_INSTR) { in marvell_nfc_naked_access_exec()
1960 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_naked_access_exec()
1962 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, in marvell_nfc_naked_access_exec()
1963 nfc->regs + NDCR); in marvell_nfc_naked_access_exec()
2185 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_exec_op()
2188 marvell_nfc_select_target(chip, op->cs); in marvell_nfc_exec_op()
2190 if (nfc->caps->is_nfcv2) in marvell_nfc_exec_op()
2206 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nand_ooblayout_ecc()
2209 return -ERANGE; in marvell_nand_ooblayout_ecc()
2211 oobregion->length = (lt->full_chunk_cnt * lt->ecc_bytes) + in marvell_nand_ooblayout_ecc()
2212 lt->last_ecc_bytes; in marvell_nand_ooblayout_ecc()
2213 oobregion->offset = mtd->oobsize - oobregion->length; in marvell_nand_ooblayout_ecc()
2222 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nand_ooblayout_free()
2225 return -ERANGE; in marvell_nand_ooblayout_free()
2231 if (mtd->writesize == SZ_4K && lt->data_bytes == SZ_2K) in marvell_nand_ooblayout_free()
2232 oobregion->offset = 6; in marvell_nand_ooblayout_free()
2234 oobregion->offset = 2; in marvell_nand_ooblayout_free()
2236 oobregion->length = (lt->full_chunk_cnt * lt->spare_bytes) + in marvell_nand_ooblayout_free()
2237 lt->last_spare_bytes - oobregion->offset; in marvell_nand_ooblayout_free()
2243 .ecc = marvell_nand_ooblayout_ecc,
2248 struct nand_ecc_ctrl *ecc) in marvell_nand_hw_ecc_controller_init() argument
2251 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nand_hw_ecc_controller_init()
2255 if (!nfc->caps->is_nfcv2 && in marvell_nand_hw_ecc_controller_init()
2256 (mtd->writesize + mtd->oobsize > MAX_CHUNK_SIZE)) { in marvell_nand_hw_ecc_controller_init()
2257 dev_err(nfc->dev, in marvell_nand_hw_ecc_controller_init()
2259 mtd->writesize, MAX_CHUNK_SIZE - mtd->oobsize); in marvell_nand_hw_ecc_controller_init()
2260 return -ENOTSUPP; in marvell_nand_hw_ecc_controller_init()
2263 to_marvell_nand(chip)->layout = NULL; in marvell_nand_hw_ecc_controller_init()
2266 if (mtd->writesize == l->writesize && in marvell_nand_hw_ecc_controller_init()
2267 ecc->size == l->chunk && ecc->strength == l->strength) { in marvell_nand_hw_ecc_controller_init()
2268 to_marvell_nand(chip)->layout = l; in marvell_nand_hw_ecc_controller_init()
2273 if (!to_marvell_nand(chip)->layout || in marvell_nand_hw_ecc_controller_init()
2274 (!nfc->caps->is_nfcv2 && ecc->strength > 1)) { in marvell_nand_hw_ecc_controller_init()
2275 dev_err(nfc->dev, in marvell_nand_hw_ecc_controller_init()
2276 "ECC strength %d at page size %d is not supported\n", in marvell_nand_hw_ecc_controller_init()
2277 ecc->strength, mtd->writesize); in marvell_nand_hw_ecc_controller_init()
2278 return -ENOTSUPP; in marvell_nand_hw_ecc_controller_init()
2281 /* Special care for the layout 2k/8-bit/512B */ in marvell_nand_hw_ecc_controller_init()
2282 if (l->writesize == 2048 && l->strength == 8) { in marvell_nand_hw_ecc_controller_init()
2283 if (mtd->oobsize < 128) { in marvell_nand_hw_ecc_controller_init()
2284 dev_err(nfc->dev, "Requested layout needs at least 128 OOB bytes\n"); in marvell_nand_hw_ecc_controller_init()
2285 return -ENOTSUPP; in marvell_nand_hw_ecc_controller_init()
2287 chip->bbt_options |= NAND_BBT_NO_OOB_BBM; in marvell_nand_hw_ecc_controller_init()
2292 ecc->steps = l->nchunks; in marvell_nand_hw_ecc_controller_init()
2293 ecc->size = l->data_bytes; in marvell_nand_hw_ecc_controller_init()
2295 if (ecc->strength == 1) { in marvell_nand_hw_ecc_controller_init()
2296 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in marvell_nand_hw_ecc_controller_init()
2297 ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw; in marvell_nand_hw_ecc_controller_init()
2298 ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page; in marvell_nand_hw_ecc_controller_init()
2299 ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw; in marvell_nand_hw_ecc_controller_init()
2300 ecc->read_oob = ecc->read_oob_raw; in marvell_nand_hw_ecc_controller_init()
2301 ecc->write_page_raw = marvell_nfc_hw_ecc_hmg_write_page_raw; in marvell_nand_hw_ecc_controller_init()
2302 ecc->write_page = marvell_nfc_hw_ecc_hmg_write_page; in marvell_nand_hw_ecc_controller_init()
2303 ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw; in marvell_nand_hw_ecc_controller_init()
2304 ecc->write_oob = ecc->write_oob_raw; in marvell_nand_hw_ecc_controller_init()
2306 chip->ecc.algo = NAND_ECC_ALGO_BCH; in marvell_nand_hw_ecc_controller_init()
2307 ecc->strength = 16; in marvell_nand_hw_ecc_controller_init()
2308 ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw; in marvell_nand_hw_ecc_controller_init()
2309 ecc->read_page = marvell_nfc_hw_ecc_bch_read_page; in marvell_nand_hw_ecc_controller_init()
2310 ecc->read_oob_raw = marvell_nfc_hw_ecc_bch_read_oob_raw; in marvell_nand_hw_ecc_controller_init()
2311 ecc->read_oob = marvell_nfc_hw_ecc_bch_read_oob; in marvell_nand_hw_ecc_controller_init()
2312 ecc->write_page_raw = marvell_nfc_hw_ecc_bch_write_page_raw; in marvell_nand_hw_ecc_controller_init()
2313 ecc->write_page = marvell_nfc_hw_ecc_bch_write_page; in marvell_nand_hw_ecc_controller_init()
2314 ecc->write_oob_raw = marvell_nfc_hw_ecc_bch_write_oob_raw; in marvell_nand_hw_ecc_controller_init()
2315 ecc->write_oob = marvell_nfc_hw_ecc_bch_write_oob; in marvell_nand_hw_ecc_controller_init()
2322 struct nand_ecc_ctrl *ecc) in marvell_nand_ecc_init() argument
2326 nanddev_get_ecc_requirements(&chip->base); in marvell_nand_ecc_init()
2327 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nand_ecc_init()
2330 if (ecc->engine_type != NAND_ECC_ENGINE_TYPE_NONE && in marvell_nand_ecc_init()
2331 (!ecc->size || !ecc->strength)) { in marvell_nand_ecc_init()
2332 if (requirements->step_size && requirements->strength) { in marvell_nand_ecc_init()
2333 ecc->size = requirements->step_size; in marvell_nand_ecc_init()
2334 ecc->strength = requirements->strength; in marvell_nand_ecc_init()
2336 dev_info(nfc->dev, in marvell_nand_ecc_init()
2337 "No minimum ECC strength, using 1b/512B\n"); in marvell_nand_ecc_init()
2338 ecc->size = 512; in marvell_nand_ecc_init()
2339 ecc->strength = 1; in marvell_nand_ecc_init()
2343 switch (ecc->engine_type) { in marvell_nand_ecc_init()
2345 ret = marvell_nand_hw_ecc_controller_init(mtd, ecc); in marvell_nand_ecc_init()
2352 if (!nfc->caps->is_nfcv2 && mtd->writesize != SZ_512 && in marvell_nand_ecc_init()
2353 mtd->writesize != SZ_2K) { in marvell_nand_ecc_init()
2354 dev_err(nfc->dev, "NFCv1 cannot write %d bytes pages\n", in marvell_nand_ecc_init()
2355 mtd->writesize); in marvell_nand_ecc_init()
2356 return -EINVAL; in marvell_nand_ecc_init()
2360 return -EINVAL; in marvell_nand_ecc_init()
2393 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_setup_interface()
2394 unsigned int period_ns = 1000000000 / clk_get_rate(nfc->core_clk) * 2; in marvell_nfc_setup_interface()
2403 if (nfc->caps->max_mode_number && nfc->caps->max_mode_number < conf->timings.mode) in marvell_nfc_setup_interface()
2404 return -EOPNOTSUPP; in marvell_nfc_setup_interface()
2407 * SDR timings are given in pico-seconds while NFC timings must be in marvell_nfc_setup_interface()
2408 * expressed in NAND controller clock cycles, which is half of the in marvell_nfc_setup_interface()
2409 * frequency of the accessible ECC clock retrieved by clk_get_rate(). in marvell_nfc_setup_interface()
2417 nfc_tmg.tRP = TO_CYCLES(DIV_ROUND_UP(sdr->tRC_min, 2), period_ns) - 1; in marvell_nfc_setup_interface()
2419 nfc_tmg.tWP = TO_CYCLES(DIV_ROUND_UP(sdr->tWC_min, 2), period_ns) - 1; in marvell_nfc_setup_interface()
2421 nfc_tmg.tCS = TO_CYCLES(sdr->tCS_min, period_ns); in marvell_nfc_setup_interface()
2422 nfc_tmg.tCH = TO_CYCLES(sdr->tCH_min, period_ns) - 1; in marvell_nfc_setup_interface()
2423 nfc_tmg.tADL = TO_CYCLES(sdr->tADL_min, period_ns); in marvell_nfc_setup_interface()
2426 * logic. With non-EDO timings, this is MIN_RD_DEL_CNT clock cycles. In in marvell_nfc_setup_interface()
2430 read_delay = sdr->tRC_min >= 30000 ? in marvell_nfc_setup_interface()
2433 nfc_tmg.tAR = TO_CYCLES(sdr->tAR_min, period_ns); in marvell_nfc_setup_interface()
2439 nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min), in marvell_nfc_setup_interface()
2440 period_ns) - 2; in marvell_nfc_setup_interface()
2441 nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min), in marvell_nfc_setup_interface()
2448 if (nfc->caps->is_nfcv2) { in marvell_nfc_setup_interface()
2449 nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns); in marvell_nfc_setup_interface()
2451 nfc_tmg.tR = TO_CYCLES64(sdr->tWB_max + sdr->tR_max, in marvell_nfc_setup_interface()
2454 nfc_tmg.tR = nfc_tmg.tCH - 3; in marvell_nfc_setup_interface()
2462 marvell_nand->ndtr0 = in marvell_nfc_setup_interface()
2471 marvell_nand->ndtr1 = in marvell_nfc_setup_interface()
2476 if (nfc->caps->is_nfcv2) { in marvell_nfc_setup_interface()
2477 marvell_nand->ndtr0 |= in marvell_nfc_setup_interface()
2482 marvell_nand->ndtr1 |= in marvell_nfc_setup_interface()
2488 * Reset nfc->selected_chip so the next command will cause the timing in marvell_nfc_setup_interface()
2491 nfc->selected_chip = NULL; in marvell_nfc_setup_interface()
2500 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nand_attach_chip()
2501 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(nfc->dev); in marvell_nand_attach_chip()
2504 if (pdata && pdata->flash_bbt) in marvell_nand_attach_chip()
2505 chip->bbt_options |= NAND_BBT_USE_FLASH; in marvell_nand_attach_chip()
2507 if (chip->bbt_options & NAND_BBT_USE_FLASH) { in marvell_nand_attach_chip()
2509 * We'll use a bad block table stored in-flash and don't in marvell_nand_attach_chip()
2512 chip->bbt_options |= NAND_BBT_NO_OOB_BBM; in marvell_nand_attach_chip()
2513 chip->bbt_td = &bbt_main_descr; in marvell_nand_attach_chip()
2514 chip->bbt_md = &bbt_mirror_descr; in marvell_nand_attach_chip()
2517 /* Save the chip-specific fields of NDCR */ in marvell_nand_attach_chip()
2518 marvell_nand->ndcr = NDCR_PAGE_SZ(mtd->writesize); in marvell_nand_attach_chip()
2519 if (chip->options & NAND_BUSWIDTH_16) in marvell_nand_attach_chip()
2520 marvell_nand->ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C; in marvell_nand_attach_chip()
2526 if (mtd->writesize <= 512) { in marvell_nand_attach_chip()
2527 marvell_nand->addr_cyc = 1; in marvell_nand_attach_chip()
2529 marvell_nand->addr_cyc = 2; in marvell_nand_attach_chip()
2530 marvell_nand->ndcr |= NDCR_RA_START; in marvell_nand_attach_chip()
2541 if (chip->options & NAND_ROW_ADDR_3) in marvell_nand_attach_chip()
2542 marvell_nand->addr_cyc += 3; in marvell_nand_attach_chip()
2544 marvell_nand->addr_cyc += 2; in marvell_nand_attach_chip()
2547 chip->ecc.size = pdata->ecc_step_size; in marvell_nand_attach_chip()
2548 chip->ecc.strength = pdata->ecc_strength; in marvell_nand_attach_chip()
2551 ret = marvell_nand_ecc_init(mtd, &chip->ecc); in marvell_nand_attach_chip()
2553 dev_err(nfc->dev, "ECC init failed: %d\n", ret); in marvell_nand_attach_chip()
2557 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { in marvell_nand_attach_chip()
2559 * Subpage write not available with hardware ECC, prohibit also in marvell_nand_attach_chip()
2562 * uncorrectable ECC errors. in marvell_nand_attach_chip()
2564 chip->options |= NAND_NO_SUBPAGE_WRITE; in marvell_nand_attach_chip()
2567 if (pdata || nfc->caps->legacy_of_bindings) { in marvell_nand_attach_chip()
2573 mtd->name = "pxa3xx_nand-0"; in marvell_nand_attach_chip()
2574 } else if (!mtd->name) { in marvell_nand_attach_chip()
2578 * should define the following property in your NAND node, ie: in marvell_nand_attach_chip()
2580 * label = "main-storage"; in marvell_nand_attach_chip()
2582 * This way, mtd->name will be set by the core when in marvell_nand_attach_chip()
2585 mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL, in marvell_nand_attach_chip()
2586 "%s:nand.%d", dev_name(nfc->dev), in marvell_nand_attach_chip()
2587 marvell_nand->sels[0].cs); in marvell_nand_attach_chip()
2588 if (!mtd->name) { in marvell_nand_attach_chip()
2589 dev_err(nfc->dev, "Failed to allocate mtd->name\n"); in marvell_nand_attach_chip()
2590 return -ENOMEM; in marvell_nand_attach_chip()
2614 * The legacy "num-cs" property indicates the number of CS on the only in marvell_nand_chip_init()
2618 * When not using legacy bindings, a couple of "reg" and "nand-rb" in marvell_nand_chip_init()
2620 * "reg" points to the CS lines and "nand-rb" to the RB line. in marvell_nand_chip_init()
2622 if (pdata || nfc->caps->legacy_of_bindings) { in marvell_nand_chip_init()
2628 return -EINVAL; in marvell_nand_chip_init()
2632 /* Alloc the nand chip structure */ in marvell_nand_chip_init()
2638 return -ENOMEM; in marvell_nand_chip_init()
2641 marvell_nand->nsels = nsels; in marvell_nand_chip_init()
2642 marvell_nand->selected_die = -1; in marvell_nand_chip_init()
2645 if (pdata || nfc->caps->legacy_of_bindings) { in marvell_nand_chip_init()
2661 if (cs >= nfc->caps->max_cs_nb) { in marvell_nand_chip_init()
2663 cs, nfc->caps->max_cs_nb); in marvell_nand_chip_init()
2664 return -EINVAL; in marvell_nand_chip_init()
2667 if (test_and_set_bit(cs, &nfc->assigned_cs)) { in marvell_nand_chip_init()
2669 return -EINVAL; in marvell_nand_chip_init()
2680 marvell_nand->sels[i].cs = cs; in marvell_nand_chip_init()
2684 marvell_nand->sels[i].ndcb0_csel = 0; in marvell_nand_chip_init()
2688 marvell_nand->sels[i].ndcb0_csel = NDCB0_CSEL; in marvell_nand_chip_init()
2691 return -EINVAL; in marvell_nand_chip_init()
2695 if (pdata || nfc->caps->legacy_of_bindings) { in marvell_nand_chip_init()
2699 ret = of_property_read_u32_index(np, "nand-rb", i, in marvell_nand_chip_init()
2709 if (rb >= nfc->caps->max_rb_nb) { in marvell_nand_chip_init()
2711 rb, nfc->caps->max_rb_nb); in marvell_nand_chip_init()
2712 return -EINVAL; in marvell_nand_chip_init()
2715 marvell_nand->sels[i].rb = rb; in marvell_nand_chip_init()
2718 chip = &marvell_nand->chip; in marvell_nand_chip_init()
2719 chip->controller = &nfc->controller; in marvell_nand_chip_init()
2722 if (of_property_read_bool(np, "marvell,nand-keep-config")) in marvell_nand_chip_init()
2723 chip->options |= NAND_KEEP_TIMINGS; in marvell_nand_chip_init()
2726 mtd->dev.parent = dev; in marvell_nand_chip_init()
2730 * ->setup_interface() is called. in marvell_nand_chip_init()
2732 marvell_nand->ndtr0 = readl_relaxed(nfc->regs + NDTR0); in marvell_nand_chip_init()
2733 marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1); in marvell_nand_chip_init()
2735 chip->options |= NAND_BUSWIDTH_AUTO; in marvell_nand_chip_init()
2737 ret = nand_scan(chip, marvell_nand->nsels); in marvell_nand_chip_init()
2739 dev_err(dev, "could not scan the nand chip\n"); in marvell_nand_chip_init()
2745 ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts); in marvell_nand_chip_init()
2754 list_add_tail(&marvell_nand->node, &nfc->chips); in marvell_nand_chip_init()
2765 list_for_each_entry_safe(entry, temp, &nfc->chips, node) { in marvell_nand_chips_cleanup()
2766 chip = &entry->chip; in marvell_nand_chips_cleanup()
2770 list_del(&entry->node); in marvell_nand_chips_cleanup()
2776 struct device_node *np = dev->of_node; in marvell_nand_chips_init()
2778 int max_cs = nfc->caps->max_cs_nb; in marvell_nand_chips_init()
2788 dev_err(dev, "too many NAND chips: %d (max = %d CS)\n", nchips, in marvell_nand_chips_init()
2790 return -EINVAL; in marvell_nand_chips_init()
2794 * Legacy bindings do not use child nodes to exhibit NAND chip in marvell_nand_chips_init()
2795 * properties and layout. Instead, NAND properties are mixed with the in marvell_nand_chips_init()
2797 * NAND controller node. in marvell_nand_chips_init()
2799 if (nfc->caps->legacy_of_bindings) { in marvell_nand_chips_init()
2822 struct platform_device *pdev = container_of(nfc->dev, in marvell_nfc_init_dma()
2830 dev_warn(nfc->dev, in marvell_nfc_init_dma()
2832 return -ENOTSUPP; in marvell_nfc_init_dma()
2835 ret = dma_set_mask_and_coherent(nfc->dev, DMA_BIT_MASK(32)); in marvell_nfc_init_dma()
2839 nfc->dma_chan = dma_request_chan(nfc->dev, "data"); in marvell_nfc_init_dma()
2840 if (IS_ERR(nfc->dma_chan)) { in marvell_nfc_init_dma()
2841 ret = PTR_ERR(nfc->dma_chan); in marvell_nfc_init_dma()
2842 nfc->dma_chan = NULL; in marvell_nfc_init_dma()
2843 return dev_err_probe(nfc->dev, ret, "DMA channel request failed\n"); in marvell_nfc_init_dma()
2848 ret = -ENXIO; in marvell_nfc_init_dma()
2854 config.src_addr = r->start + NDDB; in marvell_nfc_init_dma()
2855 config.dst_addr = r->start + NDDB; in marvell_nfc_init_dma()
2858 ret = dmaengine_slave_config(nfc->dma_chan, &config); in marvell_nfc_init_dma()
2860 dev_err(nfc->dev, "Failed to configure DMA channel\n"); in marvell_nfc_init_dma()
2870 nfc->dma_buf = kmalloc(MAX_CHUNK_SIZE, GFP_KERNEL | GFP_DMA); in marvell_nfc_init_dma()
2871 if (!nfc->dma_buf) { in marvell_nfc_init_dma()
2872 ret = -ENOMEM; in marvell_nfc_init_dma()
2876 nfc->use_dma = true; in marvell_nfc_init_dma()
2881 dma_release_channel(nfc->dma_chan); in marvell_nfc_init_dma()
2882 nfc->dma_chan = NULL; in marvell_nfc_init_dma()
2890 * ECC operations and interruptions are only enabled when specifically in marvell_nfc_reset()
2891 * needed. ECC shall not be activated in the early stages (fails probe). in marvell_nfc_reset()
2893 * SPARE_EN bit must always be set or ECC bytes will not be at the same in marvell_nfc_reset()
2897 NDCR_RD_ID_CNT(NFCV1_READID_LEN), nfc->regs + NDCR); in marvell_nfc_reset()
2898 writel_relaxed(0xFFFFFFFF, nfc->regs + NDSR); in marvell_nfc_reset()
2899 writel_relaxed(0, nfc->regs + NDECCCTRL); in marvell_nfc_reset()
2904 struct device_node *np = nfc->dev->of_node; in marvell_nfc_init()
2907 * Some SoCs like A7k/A8k need to enable manually the NAND in marvell_nfc_init()
2912 if (nfc->caps->need_system_controller) { in marvell_nfc_init()
2915 "marvell,system-controller"); in marvell_nfc_init()
2933 if (!nfc->caps->is_nfcv2) in marvell_nfc_init()
2943 struct device *dev = &pdev->dev; in marvell_nfc_probe()
2948 nfc = devm_kzalloc(&pdev->dev, sizeof(struct marvell_nfc), in marvell_nfc_probe()
2951 return -ENOMEM; in marvell_nfc_probe()
2953 nfc->dev = dev; in marvell_nfc_probe()
2954 nand_controller_init(&nfc->controller); in marvell_nfc_probe()
2955 nfc->controller.ops = &marvell_nand_controller_ops; in marvell_nfc_probe()
2956 INIT_LIST_HEAD(&nfc->chips); in marvell_nfc_probe()
2958 nfc->regs = devm_platform_ioremap_resource(pdev, 0); in marvell_nfc_probe()
2959 if (IS_ERR(nfc->regs)) in marvell_nfc_probe()
2960 return PTR_ERR(nfc->regs); in marvell_nfc_probe()
2966 nfc->core_clk = devm_clk_get(&pdev->dev, "core"); in marvell_nfc_probe()
2969 if (nfc->core_clk == ERR_PTR(-ENOENT)) in marvell_nfc_probe()
2970 nfc->core_clk = devm_clk_get(&pdev->dev, NULL); in marvell_nfc_probe()
2972 if (IS_ERR(nfc->core_clk)) in marvell_nfc_probe()
2973 return PTR_ERR(nfc->core_clk); in marvell_nfc_probe()
2975 ret = clk_prepare_enable(nfc->core_clk); in marvell_nfc_probe()
2979 nfc->reg_clk = devm_clk_get(&pdev->dev, "reg"); in marvell_nfc_probe()
2980 if (IS_ERR(nfc->reg_clk)) { in marvell_nfc_probe()
2981 if (PTR_ERR(nfc->reg_clk) != -ENOENT) { in marvell_nfc_probe()
2982 ret = PTR_ERR(nfc->reg_clk); in marvell_nfc_probe()
2986 nfc->reg_clk = NULL; in marvell_nfc_probe()
2989 ret = clk_prepare_enable(nfc->reg_clk); in marvell_nfc_probe()
2996 0, "marvell-nfc", nfc); in marvell_nfc_probe()
3000 /* Get NAND controller capabilities */ in marvell_nfc_probe()
3001 if (pdev->id_entry) in marvell_nfc_probe()
3002 nfc->caps = (void *)pdev->id_entry->driver_data; in marvell_nfc_probe()
3004 nfc->caps = of_device_get_match_data(&pdev->dev); in marvell_nfc_probe()
3006 if (!nfc->caps) { in marvell_nfc_probe()
3008 ret = -EINVAL; in marvell_nfc_probe()
3026 if (nfc->use_dma) in marvell_nfc_probe()
3027 dma_release_channel(nfc->dma_chan); in marvell_nfc_probe()
3029 clk_disable_unprepare(nfc->reg_clk); in marvell_nfc_probe()
3031 clk_disable_unprepare(nfc->core_clk); in marvell_nfc_probe()
3042 if (nfc->use_dma) { in marvell_nfc_remove()
3043 dmaengine_terminate_all(nfc->dma_chan); in marvell_nfc_remove()
3044 dma_release_channel(nfc->dma_chan); in marvell_nfc_remove()
3047 clk_disable_unprepare(nfc->reg_clk); in marvell_nfc_remove()
3048 clk_disable_unprepare(nfc->core_clk); in marvell_nfc_remove()
3056 list_for_each_entry(chip, &nfc->chips, node) in marvell_nfc_suspend()
3057 marvell_nfc_wait_ndrun(&chip->chip); in marvell_nfc_suspend()
3059 clk_disable_unprepare(nfc->reg_clk); in marvell_nfc_suspend()
3060 clk_disable_unprepare(nfc->core_clk); in marvell_nfc_suspend()
3070 ret = clk_prepare_enable(nfc->core_clk); in marvell_nfc_resume()
3074 ret = clk_prepare_enable(nfc->reg_clk); in marvell_nfc_resume()
3076 clk_disable_unprepare(nfc->core_clk); in marvell_nfc_resume()
3081 * Reset nfc->selected_chip so the next command will cause the timing in marvell_nfc_resume()
3084 nfc->selected_chip = NULL; in marvell_nfc_resume()
3146 .name = "pxa3xx-nand",
3155 .compatible = "marvell,armada-8k-nand-controller",
3159 .compatible = "marvell,ac5-nand-controller",
3163 .compatible = "marvell,armada370-nand-controller",
3167 .compatible = "marvell,pxa3xx-nand-controller",
3172 .compatible = "marvell,armada-8k-nand",
3176 .compatible = "marvell,armada370-nand",
3180 .compatible = "marvell,pxa3xx-nand",
3189 .name = "marvell-nfc",
3200 MODULE_DESCRIPTION("Marvell NAND controller driver");