Lines Matching +full:non +full:- +full:compliant

1 # SPDX-License-Identifier: GPL-2.0-only
13 	  support any device that is CFI-compliant, you need to enable this
18 	tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
22 	  This option enables JEDEC-style probing of flash chips which are not
24 	  CFI-targeted flash drivers for any chips which are identified which
26 	  covers most AMD/Fujitsu-compatible chips and also non-CFI
53 	  are expected to be wired to the CPU in 'host-endian' form.
85 	bool "Support  8-bit buswidth" if MTD_CFI_GEOMETRY
92 	bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
99 	bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
106 	bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
113 	bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
120 	bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
128 	bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
131 	  If your flash chips are not interleaved - i.e. you only have one
135 	bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
138 	  If your flash chips are interleaved in pairs - i.e. you have two
142 	bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
145 	  If your flash chips are interleaved in fours - i.e. you have four
149 	bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
152 	  If your flash chips are interleaved in eights - i.e. you have eight
156 	bool "Protection Registers aka one-time programmable (OTP) bits"
162 	  A subset of them are pre-programmed at the factory with a
163 	  unique set of values. The rest is user-programmable.
165 	  The user-programmable Protection Registers contain one-time
186 	  sets which a CFI-compliant chip may claim to implement. This code
196 	  sets which a CFI-compliant chip may claim to implement. This code
206 	  sets which a CFI-compliant chip may claim to implement. This code
232 	  with this driver will return -ENODEV upon access.