Lines Matching +full:enable +full:- +full:ssc
1 // SPDX-License-Identifier: GPL-2.0+
7 * Version: v0.9.0 (2019-08-08)
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pci.h"
326 /* enable tuning parameters control */ in gli_set_9750()
383 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
396 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
398 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
399 return -ETIMEDOUT; in __sdhci_execute_tuning_9750()
403 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
406 return -EAGAIN; in __sdhci_execute_tuning_9750()
411 host->mmc->retune_period = 0; in gl9750_execute_tuning()
412 if (host->tuning_mode == SDHCI_TUNING_MODE_1) in gl9750_execute_tuning()
413 host->mmc->retune_period = host->tuning_count; in gl9750_execute_tuning()
416 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); in gl9750_execute_tuning()
465 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm) in gl9750_set_ssc() argument
468 u32 ssc; in gl9750_set_ssc() local
472 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); in gl9750_set_ssc()
475 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; in gl9750_set_ssc()
477 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable); in gl9750_set_ssc()
478 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); in gl9750_set_ssc()
479 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); in gl9750_set_ssc()
486 bool enable = gl9750_ssc_enable(host); in gl9750_set_ssc_pll_205mhz() local
488 /* set pll to 205MHz and ssc */ in gl9750_set_ssc_pll_205mhz()
489 gl9750_set_ssc(host, enable, 0xF, 0x5A1D); in gl9750_set_ssc_pll_205mhz()
495 bool enable = gl9750_ssc_enable(host); in gl9750_set_ssc_pll_100mhz() local
497 /* set pll to 100MHz and ssc */ in gl9750_set_ssc_pll_100mhz()
498 gl9750_set_ssc(host, enable, 0xE, 0x51EC); in gl9750_set_ssc_pll_100mhz()
504 bool enable = gl9750_ssc_enable(host); in gl9750_set_ssc_pll_50mhz() local
506 /* set pll to 50MHz and ssc */ in gl9750_set_ssc_pll_50mhz()
507 gl9750_set_ssc(host, enable, 0xE, 0x51EC); in gl9750_set_ssc_pll_50mhz()
513 struct mmc_ios *ios = &host->mmc->ios; in sdhci_gl9750_set_clock()
516 host->mmc->actual_clock = 0; in sdhci_gl9750_set_clock()
524 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_gl9750_set_clock()
525 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9750_set_clock()
526 host->mmc->actual_clock = 205000000; in sdhci_gl9750_set_clock()
557 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1, in gli_pcie_enable_msi()
560 pr_warn("%s: enable PCI MSI failed, error=%d\n", in gli_pcie_enable_msi()
561 mmc_hostname(slot->host->mmc), ret); in gli_pcie_enable_msi()
565 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); in gli_pcie_enable_msi()
645 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) in gl9755_set_ssc() argument
648 u32 ssc; in gl9755_set_ssc() local
652 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); in gl9755_set_ssc()
655 ssc &= ~PCI_GLI_9755_PLLSSC_PPM; in gl9755_set_ssc()
657 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable); in gl9755_set_ssc()
658 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); in gl9755_set_ssc()
659 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); in gl9755_set_ssc()
666 bool enable = gl9755_ssc_enable(pdev); in gl9755_set_ssc_pll_205mhz() local
668 /* set pll to 205MHz and ssc */ in gl9755_set_ssc_pll_205mhz()
669 gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D); in gl9755_set_ssc_pll_205mhz()
675 bool enable = gl9755_ssc_enable(pdev); in gl9755_set_ssc_pll_100mhz() local
677 /* set pll to 100MHz and ssc */ in gl9755_set_ssc_pll_100mhz()
678 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); in gl9755_set_ssc_pll_100mhz()
684 bool enable = gl9755_ssc_enable(pdev); in gl9755_set_ssc_pll_50mhz() local
686 /* set pll to 50MHz and ssc */ in gl9755_set_ssc_pll_50mhz()
687 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); in gl9755_set_ssc_pll_50mhz()
694 struct mmc_ios *ios = &host->mmc->ios; in sdhci_gl9755_set_clock()
698 pdev = slot->chip->pdev; in sdhci_gl9755_set_clock()
699 host->mmc->actual_clock = 0; in sdhci_gl9755_set_clock()
707 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_gl9755_set_clock()
708 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9755_set_clock()
709 host->mmc->actual_clock = 205000000; in sdhci_gl9755_set_clock()
722 struct pci_dev *pdev = slot->chip->pdev; in gl9755_hw_setting()
732 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted")) in gl9755_hw_setting()
734 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted")) in gl9755_hw_setting()
740 /* enable short circuit protection */ in gl9755_hw_setting()
799 u8 enable; in gl9767_ssc_enable() local
804 enable = FIELD_GET(PCIE_GLI_9767_COM_MAILBOX_SSC_EN, value); in gl9767_ssc_enable()
808 return enable; in gl9767_ssc_enable()
811 static void gl9767_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) in gl9767_set_ssc() argument
814 u32 ssc; in gl9767_set_ssc() local
819 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc); in gl9767_set_ssc()
822 ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM; in gl9767_set_ssc()
824 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_EN, enable); in gl9767_set_ssc()
825 ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm); in gl9767_set_ssc()
826 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc); in gl9767_set_ssc()
855 bool enable = gl9767_ssc_enable(pdev); in gl9767_set_ssc_pll_205mhz() local
857 /* set pll to 205MHz and ssc */ in gl9767_set_ssc_pll_205mhz()
858 gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3); in gl9767_set_ssc_pll_205mhz()
878 struct mmc_ios *ios = &host->mmc->ios; in sdhci_gl9767_set_clock()
883 pdev = slot->chip->pdev; in sdhci_gl9767_set_clock()
884 host->mmc->actual_clock = 0; in sdhci_gl9767_set_clock()
898 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_gl9767_set_clock()
899 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9767_set_clock()
900 host->mmc->actual_clock = 205000000; in sdhci_gl9767_set_clock()
924 struct pci_dev *pdev = slot->chip->pdev; in gl9767_hw_setting()
970 pdev = slot->chip->pdev; in gl9767_init_sd_express()
972 if (mmc->ops->get_ro(mmc)) { in gl9767_init_sd_express()
973 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); in gl9767_init_sd_express()
1033 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); in gl9767_init_sd_express()
1051 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9750()
1055 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in gli_probe_slot_gl9750()
1063 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9755()
1067 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in gli_probe_slot_gl9755()
1075 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9767()
1080 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in gli_probe_slot_gl9767()
1081 host->mmc->caps2 |= MMC_CAP2_SD_EXP; in gli_probe_slot_gl9767()
1082 host->mmc_host_ops.init_sd_express = gl9767_init_sd_express; in gli_probe_slot_gl9767()
1094 * (6) Set 1.8V Signal Enable in the Host Control 2 register. in sdhci_gli_voltage_switch()
1097 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to in sdhci_gli_voltage_switch()
1100 * Wait 5ms after set 1.8V signal enable in Host Control 2 register in sdhci_gli_voltage_switch()
1101 * to ensure 1.8V signal enable bit is set by GL9750/GL9755. in sdhci_gli_voltage_switch()
1117 * (6) Set 1.8V Signal Enable in the Host Control 2 register. in sdhci_gl9767_voltage_switch()
1120 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to in sdhci_gl9767_voltage_switch()
1123 * Wait 5ms after set 1.8V signal enable in Host Control 2 register in sdhci_gl9767_voltage_switch()
1124 * to ensure 1.8V signal enable bit is set by GL9767. in sdhci_gl9767_voltage_switch()
1140 value = readl(host->ioaddr + reg); in sdhci_gl9750_readl()
1154 if (ios->enhanced_strobe) in gl9763e_hs400_enhanced_strobe()
1188 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_gl9763e_cqe_pre_enable()
1212 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_gl9763e_cqhci_irq()
1220 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_gl9763e_cqe_post_disable()
1230 .enable = sdhci_gl9763e_cqe_enable,
1239 struct device *dev = &slot->chip->pdev->dev; in gl9763e_add_host()
1240 struct sdhci_host *host = slot->host; in gl9763e_add_host()
1251 ret = -ENOMEM; in gl9763e_add_host()
1255 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR; in gl9763e_add_host()
1256 cq_host->ops = &sdhci_gl9763e_cqhci_ops; in gl9763e_add_host()
1258 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in gl9763e_add_host()
1260 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in gl9763e_add_host()
1262 ret = cqhci_init(cq_host, host->mmc, dma64); in gl9763e_add_host()
1279 struct pci_dev *pdev = slot->chip->pdev; in gli_set_gl9763e()
1313 static void gl9763e_set_low_power_negotiation(struct sdhci_pci_slot *slot, bool enable) in gl9763e_set_low_power_negotiation() argument
1315 struct pci_dev *pdev = slot->chip->pdev; in gl9763e_set_low_power_negotiation()
1325 if (enable) in gl9763e_set_low_power_negotiation()
1340 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_runtime_suspend()
1341 struct sdhci_host *host = slot->host; in gl9763e_runtime_suspend()
1344 /* Enable LPM negotiation to allow entering L1 state */ in gl9763e_runtime_suspend()
1356 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_runtime_resume()
1357 struct sdhci_host *host = slot->host; in gl9763e_runtime_resume()
1360 if (host->mmc->ios.power_mode != MMC_POWER_ON) in gl9763e_runtime_resume()
1373 mmc_hostname(host->mmc)); in gl9763e_runtime_resume()
1390 struct sdhci_pci_slot *slot = chip->slots[0]; in sdhci_pci_gli_resume()
1392 pci_free_irq_vectors(slot->chip->pdev); in sdhci_pci_gli_resume()
1400 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_resume()
1407 ret = cqhci_resume(slot->host->mmc); in gl9763e_resume()
1422 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_suspend()
1426 * Certain SoCs can suspend only with the bus in low- in gl9763e_suspend()
1428 * Re-enable LPM negotiation to allow entering L1 state in gl9763e_suspend()
1433 ret = cqhci_suspend(slot->host->mmc); in gl9763e_suspend()
1437 ret = sdhci_suspend_host(slot->host); in gl9763e_suspend()
1444 cqhci_resume(slot->host->mmc); in gl9763e_suspend()
1453 struct pci_dev *pdev = slot->chip->pdev; in gli_probe_slot_gl9763e()
1454 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9763e()
1457 host->mmc->caps |= MMC_CAP_8_BIT_DATA | in gli_probe_slot_gl9763e()
1460 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR | in gli_probe_slot_gl9763e()
1469 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in gli_probe_slot_gl9763e()
1472 host->mmc_host_ops.hs400_enhanced_strobe = in gli_probe_slot_gl9763e()
1484 u32 val = readl(host->ioaddr + (reg & ~3)); in sdhci_gli_readw()
1493 u32 val = readl(host->ioaddr + (reg & ~3)); in sdhci_gli_readb()