Lines Matching refs:MSDC_CFG
53 #define MSDC_CFG 0x0 macro
671 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); in msdc_reset_hw()
672 readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0); in msdc_reset_hw()
806 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
809 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
866 return readl_poll_timeout(host->base + MSDC_CFG, val, in msdc_ungate_clock()
884 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
891 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); in msdc_set_mclk()
893 sdr_clr_bits(host->base + MSDC_CFG, in msdc_set_mclk()
915 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
918 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
937 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
941 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
945 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
950 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); in msdc_set_mclk()
951 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
1069 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); in msdc_cmd_prepare_raw_cmd()
1701 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); in msdc_init_hw()
2918 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); in msdc_save_reg()
2946 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); in msdc_restore_reg()