Lines Matching defs:msdc_host
419 struct msdc_host { struct
420 struct device *dev;
421 const struct mtk_mmc_compatible *dev_comp;
422 int cmd_rsp;
424 spinlock_t lock;
425 struct mmc_request *mrq;
426 struct mmc_command *cmd;
427 struct mmc_data *data;
428 int error;
430 void __iomem *base; /* host base address */
431 void __iomem *top_base; /* host top register base address */
433 struct msdc_dma dma; /* dma channel */
434 u64 dma_mask;
436 u32 timeout_ns; /* data timeout ns */
437 u32 timeout_clks; /* data timeout clks */
439 struct pinctrl *pinctrl;
440 struct pinctrl_state *pins_default;
441 struct pinctrl_state *pins_uhs;
442 struct pinctrl_state *pins_eint;
443 struct delayed_work req_timeout;
444 int irq; /* host interrupt */
445 int eint_irq; /* interrupt from sdio device for waking up system */
446 struct reset_control *reset;
448 struct clk *src_clk; /* msdc source clock */
449 struct clk *h_clk; /* msdc h_clk */
450 struct clk *bus_clk; /* bus clock which used to access register */
451 struct clk *src_clk_cg; /* msdc source clock control gate */
452 struct clk *sys_clk_cg; /* msdc subsys clock control gate */
453 struct clk *crypto_clk; /* msdc crypto clock control gate */
454 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
455 u32 mclk; /* mmc subsystem clock frequency */
456 u32 src_clk_freq; /* source clock frequency */
457 unsigned char timing;
458 bool vqmmc_enabled;
459 u32 latch_ck;
460 u32 hs400_ds_delay;
461 u32 hs400_ds_dly3;
462 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
463 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
464 bool hs400_cmd_resp_sel_rising;
466 bool hs400_mode; /* current eMMC will run at hs400 mode */
467 bool hs400_tuning; /* hs400 mode online tuning */
468 bool internal_cd; /* Use internal card-detect logic */
469 bool cqhci; /* support eMMC hw cmdq */
470 struct msdc_save_para save_para; /* used when gate HCLK */
471 struct msdc_tune_para def_tune_para; /* default tune setting */
472 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
473 struct cqhci_host *cq_host;
474 u32 cq_ssc1_time;