29 		{0x96, 0x96, 0x96},  in rts5261_fill_driving()
30 		{0x96, 0x96, 0x96},  in rts5261_fill_driving()
31 		{0x7F, 0x7F, 0x7F},  in rts5261_fill_driving()
32 		{0x13, 0x13, 0x13},  in rts5261_fill_driving()
35 		{0xB3, 0xB3, 0xB3},  in rts5261_fill_driving()
36 		{0x3A, 0x3A, 0x3A},  in rts5261_fill_driving()
37 		{0xE6, 0xE6, 0xE6},  in rts5261_fill_driving()
38 		{0x99, 0x99, 0x99},  in rts5261_fill_driving()
51 			 0xFF, driving[drive_sel][0]);  in rts5261_fill_driving()
54 			 0xFF, driving[drive_sel][1]);  in rts5261_fill_driving()
57 			 0xFF, driving[drive_sel][2]);  in rts5261_fill_driving()
62 	/* Set relink_time to 0 */  in rts5261_force_power_down()
63 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);  in rts5261_force_power_down()
64 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);  in rts5261_force_power_down()
66 				RELINK_TIME_MASK, 0);  in rts5261_force_power_down()
74 				CD_RESUME_EN_MASK, 0);  in rts5261_force_power_down()
75 		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);  in rts5261_force_power_down()
81 				FORCE_PM_CONTROL | FORCE_PM_VALUE, 0);  in rts5261_force_power_down()
109 		0x02, 0x02);  in rts5261_turn_on_led()
115 		0x02, 0x00);  in rts5261_turn_off_led()
119  *     SD_DAT[3:0] ==> pull up
126 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
127 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
128 	0,
132  *     SD_DAT[3:0] ==> pull down
139 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
140 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
141 	0,
149 	rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,  in rts5261_sd_set_sample_push_timing_sd30()
151 	rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);  in rts5261_sd_set_sample_push_timing_sd30()
153 	return 0;  in rts5261_sd_set_sample_push_timing_sd30()
179 	rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,  in rts5261_card_power_on()
183 			0xFF, SD20_RX_POS_EDGE);  in rts5261_card_power_on()
184 	rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);  in rts5261_card_power_on()
189 	rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);  in rts5261_card_power_on()
192 			SD30_CLK_STOP_CFG0, 0);  in rts5261_card_power_on()
198 	return 0;  in rts5261_card_power_on()
204 	u16 val = 0;  in rts5261_switch_output_voltage()
214 		if (err < 0)  in rts5261_switch_output_voltage()
220 				SD_IO_USING_1V8, 0);  in rts5261_switch_output_voltage()
226 		if (err < 0)  in rts5261_switch_output_voltage()
241 	return 0;  in rts5261_switch_output_voltage()
263 	u8 val = 0;  in rts5261_enable_ocp()
269 	rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);  in rts5261_enable_ocp()
275 	u8 mask = 0;  in rts5261_disable_ocp()
278 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);  in rts5261_disable_ocp()
280 			RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);  in rts5261_disable_ocp()
286 	int err = 0;  in rts5261_card_power_off()
290 				RTS5261_LDO_POWERON_MASK, 0);  in rts5261_card_power_off()
293 		CFG_SD_POW_AUTO_PD, 0);  in rts5261_card_power_off()
325 			RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);  in rts5261_init_ocp()
331 	u8 mask = 0;  in rts5261_clear_ocpstat()
332 	u8 val = 0;  in rts5261_clear_ocpstat()
340 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);  in rts5261_clear_ocpstat()
354 		rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);  in rts5261_process_ocp()
355 		pcr->ocp_stat = 0;  in rts5261_process_ocp()
372 		RTS5261_EFUSE_ADDR_MASK, 0x00);  in rts5261_init_from_hw()
378 	for (i = 0; i < MAX_RW_REG_CNT; i++) {  in rts5261_init_from_hw()
380 		if ((tmp & 0x80) == 0)  in rts5261_init_from_hw()
384 	efuse_valid = ((tmp & 0x0C) >> 2);  in rts5261_init_from_hw()
385 	pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);  in rts5261_init_from_hw()
388 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, lval2);  in rts5261_init_from_hw()
389 	/* 0x816 */  in rts5261_init_from_hw()
390 	valid = (u8)((lval2 >> 16) & 0x03);  in rts5261_init_from_hw()
393 		REG_EFUSE_POR, 0);  in rts5261_init_from_hw()
406 	} else if (efuse_valid == 0) {  in rts5261_init_from_hw()
415 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg2, lval2);  in rts5261_init_from_hw()
433 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg1, lval1);  in rts5261_init_from_hw()
441 		rtsx_pci_write_register(pcr, 0xFF0C, 0xFF, (u8)(lval1 & 0xFF));  in rts5261_init_from_hw()
442 		rtsx_pci_write_register(pcr, 0xFF0D, 0xFF, (u8)((lval1 >> 8) & 0xFF));  in rts5261_init_from_hw()
443 		rtsx_pci_write_register(pcr, 0xFF0E, 0xFF, (u8)((lval1 >> 16) & 0xFF));  in rts5261_init_from_hw()
444 		rtsx_pci_write_register(pcr, 0xFF0F, 0xFF, (u8)((lval1 >> 24) & 0xFF));  in rts5261_init_from_hw()
445 		rtsx_pci_write_register(pcr, 0xFF10, 0xFF, (u8)(lval2 & 0xFF));  in rts5261_init_from_hw()
446 		rtsx_pci_write_register(pcr, 0xFF11, 0xFF, (u8)((lval2 >> 8) & 0xFF));  in rts5261_init_from_hw()
447 		rtsx_pci_write_register(pcr, 0xFF12, 0xFF, (u8)((lval2 >> 16) & 0xFF));  in rts5261_init_from_hw()
450 		lval2 = lval2 & 0x00FFFFFF;  in rts5261_init_from_hw()
481 	rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);  in rts5261_extra_init_hw()
485 		rtsx_pci_writel(pcr, RTSX_DUM_REG, val | 0x1);  in rts5261_extra_init_hw()
488 			RTS5261_AUX_CLK_16M_EN, 0);  in rts5261_extra_init_hw()
492 			RTS5261_FORCE_PRSNT_LOW, 0);  in rts5261_extra_init_hw()
503 	rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);  in rts5261_extra_init_hw()
509 		rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);  in rts5261_extra_init_hw()
511 		rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);  in rts5261_extra_init_hw()
524 	rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);  in rts5261_extra_init_hw()
527 		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01);  in rts5261_extra_init_hw()
532 		rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);  in rts5261_extra_init_hw()
536 	rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00);  in rts5261_extra_init_hw()
540 		RTS5261_INFORM_RTD3_COLD, 0);  in rts5261_extra_init_hw()
542 	return 0;  in rts5261_extra_init_hw()
553 	val |= (pcr->aspm_en & 0x02);  in rts5261_enable_aspm()
569 					   PCI_EXP_LNKCTL_ASPMC, 0);  in rts5261_disable_aspm()
571 	rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);  in rts5261_disable_aspm()
588 	u8 val = 0;  in rts5261_set_l1off_cfg_sub_d0()
658 	if (err < 0)  in rts5261_pci_switch_clock()
671 		return 0;  in rts5261_pci_switch_clock()
722 		ssc_depth = 0;  in rts5261_pci_switch_clock()
730 			0xFF, (div << 4) | mcu_cnt);  in rts5261_pci_switch_clock()
731 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);  in rts5261_pci_switch_clock()
734 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);  in rts5261_pci_switch_clock()
738 				PHASE_NOT_RESET, 0);  in rts5261_pci_switch_clock()
740 				PHASE_NOT_RESET, 0);  in rts5261_pci_switch_clock()
748 	if (err < 0)  in rts5261_pci_switch_clock()
753 	err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);  in rts5261_pci_switch_clock()
754 	if (err < 0)  in rts5261_pci_switch_clock()
758 	return 0;  in rts5261_pci_switch_clock()
775 	pcr->flags = 0;  in rts5261_init_params()
777 	pcr->sd30_drive_sel_1v8 = 0x00;  in rts5261_init_params()
778 	pcr->sd30_drive_sel_3v3 = 0x00;  in rts5261_init_params()
799 	option->ltr_l1off_sspwrgate = 0x7F;  in rts5261_init_params()
800 	option->ltr_l1off_snooze_sspwrgate = 0x78;  in rts5261_init_params()