864 		ccfifo_writel(emc, 1, EMC_SELF_REF, 0);  in tegra210_emc_r21021_set_clock()
1264 			ccfifo_writel(emc, 0x101, EMC_SELF_REF, 0);  in tegra210_emc_r21021_set_clock()
1266 			ccfifo_writel(emc, 0x1, EMC_SELF_REF, 0);  in tegra210_emc_r21021_set_clock()
1270 			ccfifo_writel(emc, mr13_flip_fspwr ^ 0x40, EMC_MRW3, 0);  in tegra210_emc_r21021_set_clock()
1271 			ccfifo_writel(emc, (next->burst_regs[EMC_MRW6_INDEX] &  in tegra210_emc_r21021_set_clock()
1275 			ccfifo_writel(emc, (next->burst_regs[EMC_MRW14_INDEX] &  in tegra210_emc_r21021_set_clock()
1281 				ccfifo_writel(emc,  in tegra210_emc_r21021_set_clock()
1286 				ccfifo_writel(emc,  in tegra210_emc_r21021_set_clock()
1295 					ccfifo_writel(emc,  in tegra210_emc_r21021_set_clock()
1300 					ccfifo_writel(emc,  in tegra210_emc_r21021_set_clock()
1305 					ccfifo_writel(emc,  in tegra210_emc_r21021_set_clock()
1314 		ccfifo_writel(emc, mr13_flip_fspop | 0x8, EMC_MRW3, value);  in tegra210_emc_r21021_set_clock()
1315 		ccfifo_writel(emc, 0, 0, tFC_lpddr4 / src_clk_period);  in tegra210_emc_r21021_set_clock()
1327 		ccfifo_writel(emc, emc_pin & ~(EMC_PIN_PIN_CKE_PER_DEV |  in tegra210_emc_r21021_set_clock()
1359 	ccfifo_writel(emc, 0x0, EMC_CFG_SYNC, delay);  in tegra210_emc_r21021_set_clock()
1362 	ccfifo_writel(emc, value, EMC_DBG, 0);  in tegra210_emc_r21021_set_clock()
1373 	ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE, 0);  in tegra210_emc_r21021_set_clock()
1375 	ccfifo_writel(emc, value, EMC_DBG, 0);  in tegra210_emc_r21021_set_clock()
1384 	ccfifo_writel(emc, emc_dbg, EMC_DBG, 0);  in tegra210_emc_r21021_set_clock()
1400 		ccfifo_writel(emc, value, EMC_PIN, 0);  in tegra210_emc_r21021_set_clock()
1433 				ccfifo_writel(emc,  in tegra210_emc_r21021_set_clock()
1439 			ccfifo_writel(emc, value, EMC_MRW3, delay);  in tegra210_emc_r21021_set_clock()
1440 			ccfifo_writel(emc, 0, EMC_SELF_REF, 0);  in tegra210_emc_r21021_set_clock()
1441 			ccfifo_writel(emc, 0, EMC_REF, 0);  in tegra210_emc_r21021_set_clock()
1442 			ccfifo_writel(emc, 2UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |  in tegra210_emc_r21021_set_clock()
1448 				ccfifo_writel(emc,  in tegra210_emc_r21021_set_clock()
1453 			ccfifo_writel(emc, 2UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |  in tegra210_emc_r21021_set_clock()
1457 			ccfifo_writel(emc, 1UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |  in tegra210_emc_r21021_set_clock()
1462 			ccfifo_writel(emc, value, EMC_MRW3, 0);  in tegra210_emc_r21021_set_clock()
1463 			ccfifo_writel(emc, 0, EMC_SELF_REF, 0);  in tegra210_emc_r21021_set_clock()
1464 			ccfifo_writel(emc, 0, EMC_REF, 0);  in tegra210_emc_r21021_set_clock()
1466 			ccfifo_writel(emc, 1UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |  in tegra210_emc_r21021_set_clock()
1471 				ccfifo_writel(emc, EMC_ZQ_CAL_ZQ_CAL_CMD,  in tegra210_emc_r21021_set_clock()
1475 			ccfifo_writel(emc, value, EMC_MRW3, delay);  in tegra210_emc_r21021_set_clock()
1476 			ccfifo_writel(emc, 0, EMC_SELF_REF, 0);  in tegra210_emc_r21021_set_clock()
1477 			ccfifo_writel(emc, 0, EMC_REF, 0);  in tegra210_emc_r21021_set_clock()
1479 			ccfifo_writel(emc, EMC_ZQ_CAL_ZQ_LATCH_CMD, EMC_ZQ_CAL,  in tegra210_emc_r21021_set_clock()
1485 	ccfifo_writel(emc, 0, 0, 10);  in tegra210_emc_r21021_set_clock()
1499 		ccfifo_writel(emc, 0, EMC_SELF_REF, 0);  in tegra210_emc_r21021_set_clock()
1508 		ccfifo_writel(emc, next->emc_mrw2, EMC_MRW2, 0);  in tegra210_emc_r21021_set_clock()
1509 		ccfifo_writel(emc, next->emc_mrw,  EMC_MRW,  0);  in tegra210_emc_r21021_set_clock()
1511 			ccfifo_writel(emc, next->emc_mrw4, EMC_MRW4, 0);  in tegra210_emc_r21021_set_clock()
1514 			ccfifo_writel(emc, next->emc_emrs &  in tegra210_emc_r21021_set_clock()
1516 		ccfifo_writel(emc, next->emc_emrs2 &  in tegra210_emc_r21021_set_clock()
1518 		ccfifo_writel(emc, next->emc_mrs |  in tegra210_emc_r21021_set_clock()
1536 			ccfifo_writel(emc, value, EMC_MRS_WAIT_CNT2, 0);  in tegra210_emc_r21021_set_clock()
1539 			ccfifo_writel(emc, 2 << EMC_MRW_MRW_DEV_SELECTN_SHIFT |  in tegra210_emc_r21021_set_clock()
1550 				ccfifo_writel(emc, value, EMC_MRW, 0);  in tegra210_emc_r21021_set_clock()
1555 			ccfifo_writel(emc, value |  in tegra210_emc_r21021_set_clock()
1563 				ccfifo_writel(emc, value, EMC_ZQ_CAL, 0);  in tegra210_emc_r21021_set_clock()
1576 		ccfifo_writel(emc,  in tegra210_emc_r21021_set_clock()
1589 		ccfifo_writel(emc, 0, EMC_REF, 0);  in tegra210_emc_r21021_set_clock()
1592 		ccfifo_writel(emc, 1, EMC_ISSUE_QRST, 0);  in tegra210_emc_r21021_set_clock()
1593 		ccfifo_writel(emc, 0, EMC_ISSUE_QRST, 2);  in tegra210_emc_r21021_set_clock()
1603 		ccfifo_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE,  in tegra210_emc_r21021_set_clock()
1606 			ccfifo_writel(emc, next->burst_regs[EMC_ZCAL_INTERVAL_INDEX],  in tegra210_emc_r21021_set_clock()
1610 			ccfifo_writel(emc, next->burst_regs[EMC_CFG_INDEX] &  in tegra210_emc_r21021_set_clock()
1613 		ccfifo_writel(emc, emc_dbg, EMC_DBG, 0);  in tegra210_emc_r21021_set_clock()
1622 	ccfifo_writel(emc, emc_cfg_pipe_clk, EMC_CFG_PIPE_CLK, 0);  in tegra210_emc_r21021_set_clock()