Lines Matching full:sid
74 unsigned int sid) in tegra186_mc_client_sid_override() argument
78 value = readl(mc->regs + client->regs.sid.security); in tegra186_mc_client_sid_override()
97 writel(value, mc->regs + client->regs.sid.security); in tegra186_mc_client_sid_override()
100 value = readl(mc->regs + client->regs.sid.override); in tegra186_mc_client_sid_override()
103 if (old != sid) { in tegra186_mc_client_sid_override()
104 dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old, in tegra186_mc_client_sid_override()
105 client->name, sid); in tegra186_mc_client_sid_override()
106 writel(sid, mc->regs + client->regs.sid.override); in tegra186_mc_client_sid_override()
125 u32 sid = fwspec->ids[0] & MC_SID_STREAMID_OVERRIDE_MASK; in tegra186_mc_probe_device() local
127 tegra186_mc_client_sid_override(mc, client, sid); in tegra186_mc_probe_device()
151 .sid = TEGRA186_SID_PASSTHROUGH,
153 .sid = {
161 .sid = TEGRA186_SID_AFI,
163 .sid = {
171 .sid = TEGRA186_SID_HDA,
173 .sid = {
181 .sid = TEGRA186_SID_HOST1X,
183 .sid = {
191 .sid = TEGRA186_SID_NVENC,
193 .sid = {
201 .sid = TEGRA186_SID_SATA,
203 .sid = {
211 .sid = TEGRA186_SID_PASSTHROUGH,
213 .sid = {
221 .sid = TEGRA186_SID_NVENC,
223 .sid = {
231 .sid = TEGRA186_SID_AFI,
233 .sid = {
241 .sid = TEGRA186_SID_HDA,
243 .sid = {
251 .sid = TEGRA186_SID_PASSTHROUGH,
253 .sid = {
261 .sid = TEGRA186_SID_SATA,
263 .sid = {
271 .sid = TEGRA186_SID_ISP,
273 .sid = {
281 .sid = TEGRA186_SID_ISP,
283 .sid = {
291 .sid = TEGRA186_SID_ISP,
293 .sid = {
301 .sid = TEGRA186_SID_XUSB_HOST,
303 .sid = {
311 .sid = TEGRA186_SID_XUSB_HOST,
313 .sid = {
321 .sid = TEGRA186_SID_XUSB_DEV,
323 .sid = {
331 .sid = TEGRA186_SID_XUSB_DEV,
333 .sid = {
341 .sid = TEGRA186_SID_TSEC,
343 .sid = {
351 .sid = TEGRA186_SID_TSEC,
353 .sid = {
361 .sid = TEGRA186_SID_GPU,
363 .sid = {
371 .sid = TEGRA186_SID_GPU,
373 .sid = {
381 .sid = TEGRA186_SID_SDMMC1,
383 .sid = {
391 .sid = TEGRA186_SID_SDMMC2,
393 .sid = {
401 .sid = TEGRA186_SID_SDMMC3,
403 .sid = {
411 .sid = TEGRA186_SID_SDMMC4,
413 .sid = {
421 .sid = TEGRA186_SID_SDMMC1,
423 .sid = {
431 .sid = TEGRA186_SID_SDMMC2,
433 .sid = {
441 .sid = TEGRA186_SID_SDMMC3,
443 .sid = {
451 .sid = TEGRA186_SID_SDMMC4,
453 .sid = {
461 .sid = TEGRA186_SID_VIC,
463 .sid = {
471 .sid = TEGRA186_SID_VIC,
473 .sid = {
481 .sid = TEGRA186_SID_VI,
483 .sid = {
491 .sid = TEGRA186_SID_NVDEC,
493 .sid = {
501 .sid = TEGRA186_SID_NVDEC,
503 .sid = {
511 .sid = TEGRA186_SID_APE,
513 .sid = {
521 .sid = TEGRA186_SID_APE,
523 .sid = {
531 .sid = TEGRA186_SID_NVJPG,
533 .sid = {
541 .sid = TEGRA186_SID_NVJPG,
543 .sid = {
551 .sid = TEGRA186_SID_SE,
553 .sid = {
561 .sid = TEGRA186_SID_SE,
563 .sid = {
571 .sid = TEGRA186_SID_ETR,
573 .sid = {
581 .sid = TEGRA186_SID_ETR,
583 .sid = {
591 .sid = TEGRA186_SID_TSECB,
593 .sid = {
601 .sid = TEGRA186_SID_TSECB,
603 .sid = {
611 .sid = TEGRA186_SID_GPU,
613 .sid = {
621 .sid = TEGRA186_SID_GPU,
623 .sid = {
631 .sid = TEGRA186_SID_GPCDMA_0,
633 .sid = {
641 .sid = TEGRA186_SID_GPCDMA_0,
643 .sid = {
651 .sid = TEGRA186_SID_EQOS,
653 .sid = {
661 .sid = TEGRA186_SID_EQOS,
663 .sid = {
671 .sid = TEGRA186_SID_UFSHC,
673 .sid = {
681 .sid = TEGRA186_SID_UFSHC,
683 .sid = {
691 .sid = TEGRA186_SID_NVDISPLAY,
693 .sid = {
701 .sid = TEGRA186_SID_BPMP,
703 .sid = {
711 .sid = TEGRA186_SID_BPMP,
713 .sid = {
721 .sid = TEGRA186_SID_BPMP,
723 .sid = {
731 .sid = TEGRA186_SID_BPMP,
733 .sid = {
741 .sid = TEGRA186_SID_AON,
743 .sid = {
751 .sid = TEGRA186_SID_AON,
753 .sid = {
761 .sid = TEGRA186_SID_AON,
763 .sid = {
771 .sid = TEGRA186_SID_AON,
773 .sid = {
781 .sid = TEGRA186_SID_SCE,
783 .sid = {
791 .sid = TEGRA186_SID_SCE,
793 .sid = {
801 .sid = TEGRA186_SID_SCE,
803 .sid = {
811 .sid = TEGRA186_SID_SCE,
813 .sid = {
821 .sid = TEGRA186_SID_APE,
823 .sid = {
831 .sid = TEGRA186_SID_APE,
833 .sid = {
841 .sid = TEGRA186_SID_NVDISPLAY,
843 .sid = {
851 .sid = TEGRA186_SID_VIC,
853 .sid = {
861 .sid = TEGRA186_SID_NVDEC,
863 .sid = {