Lines Matching +full:0 +full:x1ff
31 #define VPU_PP_IN_YUYV 0x0
32 #define VPU_PP_IN_NV12 0x1
33 #define VPU_PP_IN_YUV420 0x2
34 #define VPU_PP_IN_YUV240_TILED 0x5
35 #define VPU_PP_OUT_RGB 0x0
36 #define VPU_PP_OUT_YUYV 0x3
39 .pipeline_en = {G1_REG_PP_INTERRUPT, 1, 0x1},
40 .max_burst = {G1_REG_PP_DEV_CONFIG, 0, 0x1f},
41 .clk_gate = {G1_REG_PP_DEV_CONFIG, 1, 0x1},
42 .out_swap32 = {G1_REG_PP_DEV_CONFIG, 5, 0x1},
43 .out_endian = {G1_REG_PP_DEV_CONFIG, 6, 0x1},
44 .out_luma_base = {G1_REG_PP_OUT_LUMA_BASE, 0, 0xffffffff},
45 .input_width = {G1_REG_PP_INPUT_SIZE, 0, 0x1ff},
46 .input_height = {G1_REG_PP_INPUT_SIZE, 9, 0x1ff},
47 .output_width = {G1_REG_PP_CONTROL, 4, 0x7ff},
48 .output_height = {G1_REG_PP_CONTROL, 15, 0x7ff},
49 .input_fmt = {G1_REG_PP_CONTROL, 29, 0x7},
50 .output_fmt = {G1_REG_PP_CONTROL, 26, 0x7},
51 .orig_width = {G1_REG_PP_MASK1_ORIG_WIDTH, 23, 0x1ff},
52 .display_width = {G1_REG_PP_DISPLAY_WIDTH, 0, 0xfff},
75 HANTRO_PP_REG_WRITE(vpu, pipeline_en, 0x1); in hantro_postproc_g1_enable()
86 dst_pp_fmt = 0; in hantro_postproc_g1_enable()
91 dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); in hantro_postproc_g1_enable()
93 HANTRO_PP_REG_WRITE(vpu, clk_gate, 0x1); in hantro_postproc_g1_enable()
94 HANTRO_PP_REG_WRITE(vpu, out_endian, 0x1); in hantro_postproc_g1_enable()
95 HANTRO_PP_REG_WRITE(vpu, out_swap32, 0x1); in hantro_postproc_g1_enable()
111 return 0; in down_scale_factor()
126 dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); in hantro_postproc_g2_enable()
127 chroma_offset = ctx->dst_fmt.plane_fmt[0].bytesperline * in hantro_postproc_g2_enable()
143 u8 pp_shift = 0; in hantro_postproc_g2_enable()
151 hantro_reg_write(vpu, &g2_output_8_bits, out_depth > 8 ? 0 : 1); in hantro_postproc_g2_enable()
152 hantro_reg_write(vpu, &g2_output_format, out_depth > 8 ? 1 : 0); in hantro_postproc_g2_enable()
161 * G2 scaler can scale down by 0, 2, 4 or 8 in hantro_postproc_g2_enum_framesizes()
174 return 0; in hantro_postproc_g2_enum_framesizes()
182 for (i = 0; i < VB2_MAX_FRAME; ++i) { in hantro_postproc_free()
210 buf_size = pix_mp.plane_fmt[0].sizeimage; in hantro_postproc_alloc()
224 for (i = 0; i < num_buffers; ++i) { in hantro_postproc_alloc()
238 return 0; in hantro_postproc_alloc()
245 HANTRO_PP_REG_WRITE(vpu, pipeline_en, 0x0); in hantro_postproc_g1_disable()
252 hantro_reg_write(vpu, &g2_out_rs_e, 0); in hantro_postproc_g2_disable()