Lines Matching +full:0 +full:x1f
16 #define VPE_PID 0x0000
17 #define VPE_PID_MINOR_MASK 0x3f
18 #define VPE_PID_MINOR_SHIFT 0
19 #define VPE_PID_CUSTOM_MASK 0x03
21 #define VPE_PID_MAJOR_MASK 0x07
23 #define VPE_PID_RTL_MASK 0x1f
25 #define VPE_PID_FUNC_MASK 0xfff
27 #define VPE_PID_SCHEME_MASK 0x03
30 #define VPE_SYSCONFIG 0x0010
31 #define VPE_SYSCONFIG_IDLE_MASK 0x03
33 #define VPE_SYSCONFIG_STANDBY_MASK 0x03
35 #define VPE_FORCE_IDLE_MODE 0
39 #define VPE_FORCE_STANDBY_MODE 0
44 #define VPE_INT0_STATUS0_RAW_SET 0x0020
46 #define VPE_INT0_STATUS0_CLR 0x0028
48 #define VPE_INT0_ENABLE0_SET 0x0030
50 #define VPE_INT0_ENABLE0_CLR 0x0038
51 #define VPE_INT0_LIST0_COMPLETE BIT(0)
70 #define VPE_INT0_STATUS1_RAW_SET 0x0024
72 #define VPE_INT0_STATUS1_CLR 0x002c
74 #define VPE_INT0_ENABLE1_SET 0x0034
76 #define VPE_INT0_ENABLE1_CLR 0x003c
77 #define VPE_INT0_CHANNEL_GROUP0 BIT(0)
87 #define VPE_INTC_EOI 0x00a0
89 #define VPE_CLK_ENABLE 0x0100
90 #define VPE_VPEDMA_CLK_ENABLE BIT(0)
93 #define VPE_CLK_RESET 0x0104
94 #define VPE_VPDMA_CLK_RESET_MASK 0x1
95 #define VPE_VPDMA_CLK_RESET_SHIFT 0
96 #define VPE_DATA_PATH_CLK_RESET_MASK 0x1
98 #define VPE_MAIN_RESET_MASK 0x1
101 #define VPE_CLK_FORMAT_SELECT 0x010c
102 #define VPE_CSC_SRC_SELECT_MASK 0x03
103 #define VPE_CSC_SRC_SELECT_SHIFT 0
105 #define VPE_DS_SRC_SELECT_MASK 0x07
113 #define VPE_CLK_RANGE_MAP 0x011c
114 #define VPE_RANGE_RANGE_MAP_Y_MASK 0x07
115 #define VPE_RANGE_RANGE_MAP_Y_SHIFT 0
116 #define VPE_RANGE_RANGE_MAP_UV_MASK 0x07
122 #define VPE_US1_R0 0x0304
123 #define VPE_US2_R0 0x0404
124 #define VPE_US3_R0 0x0504
125 #define VPE_US_C1_MASK 0x3fff
127 #define VPE_US_C0_MASK 0x3fff
129 #define VPE_US_MODE_MASK 0x03
131 #define VPE_ANCHOR_FID0_C1_MASK 0x3fff
133 #define VPE_ANCHOR_FID0_C0_MASK 0x3fff
136 #define VPE_US1_R1 0x0308
137 #define VPE_US2_R1 0x0408
138 #define VPE_US3_R1 0x0508
139 #define VPE_ANCHOR_FID0_C3_MASK 0x3fff
141 #define VPE_ANCHOR_FID0_C2_MASK 0x3fff
144 #define VPE_US1_R2 0x030c
145 #define VPE_US2_R2 0x040c
146 #define VPE_US3_R2 0x050c
147 #define VPE_INTERP_FID0_C1_MASK 0x3fff
149 #define VPE_INTERP_FID0_C0_MASK 0x3fff
152 #define VPE_US1_R3 0x0310
153 #define VPE_US2_R3 0x0410
154 #define VPE_US3_R3 0x0510
155 #define VPE_INTERP_FID0_C3_MASK 0x3fff
157 #define VPE_INTERP_FID0_C2_MASK 0x3fff
160 #define VPE_US1_R4 0x0314
161 #define VPE_US2_R4 0x0414
162 #define VPE_US3_R4 0x0514
163 #define VPE_ANCHOR_FID1_C1_MASK 0x3fff
165 #define VPE_ANCHOR_FID1_C0_MASK 0x3fff
168 #define VPE_US1_R5 0x0318
169 #define VPE_US2_R5 0x0418
170 #define VPE_US3_R5 0x0518
171 #define VPE_ANCHOR_FID1_C3_MASK 0x3fff
173 #define VPE_ANCHOR_FID1_C2_MASK 0x3fff
176 #define VPE_US1_R6 0x031c
177 #define VPE_US2_R6 0x041c
178 #define VPE_US3_R6 0x051c
179 #define VPE_INTERP_FID1_C1_MASK 0x3fff
181 #define VPE_INTERP_FID1_C0_MASK 0x3fff
184 #define VPE_US1_R7 0x0320
185 #define VPE_US2_R7 0x0420
186 #define VPE_US3_R7 0x0520
187 #define VPE_INTERP_FID0_C3_MASK 0x3fff
189 #define VPE_INTERP_FID0_C2_MASK 0x3fff
193 #define VPE_DEI_FRAME_SIZE 0x0600
194 #define VPE_DEI_WIDTH_MASK 0x07ff
195 #define VPE_DEI_WIDTH_SHIFT 0
196 #define VPE_DEI_HEIGHT_MASK 0x07ff
202 #define VPE_MDT_BYPASS 0x0604
203 #define VPE_MDT_TEMPMAX_BYPASS BIT(0)
206 #define VPE_MDT_SF_THRESHOLD 0x0608
207 #define VPE_MDT_SF_SC_THR1_MASK 0xff
208 #define VPE_MDT_SF_SC_THR1_SHIFT 0
209 #define VPE_MDT_SF_SC_THR2_MASK 0xff
210 #define VPE_MDT_SF_SC_THR2_SHIFT 0
211 #define VPE_MDT_SF_SC_THR3_MASK 0xff
212 #define VPE_MDT_SF_SC_THR3_SHIFT 0
214 #define VPE_EDI_CONFIG 0x060c
215 #define VPE_EDI_INP_MODE_MASK 0x03
216 #define VPE_EDI_INP_MODE_SHIFT 0
219 #define VPE_EDI_CHROMA3D_COR_THR_MASK 0xff
221 #define VPE_EDI_DIR_COR_LOWER_THR_MASK 0xff
223 #define VPE_EDI_COR_SCALE_FACTOR_MASK 0xff
226 #define VPE_DEI_EDI_LUT_R0 0x0610
227 #define VPE_EDI_LUT0_MASK 0x1f
228 #define VPE_EDI_LUT0_SHIFT 0
229 #define VPE_EDI_LUT1_MASK 0x1f
231 #define VPE_EDI_LUT2_MASK 0x1f
233 #define VPE_EDI_LUT3_MASK 0x1f
236 #define VPE_DEI_EDI_LUT_R1 0x0614
237 #define VPE_EDI_LUT0_MASK 0x1f
238 #define VPE_EDI_LUT0_SHIFT 0
239 #define VPE_EDI_LUT1_MASK 0x1f
241 #define VPE_EDI_LUT2_MASK 0x1f
243 #define VPE_EDI_LUT3_MASK 0x1f
246 #define VPE_DEI_EDI_LUT_R2 0x0618
247 #define VPE_EDI_LUT4_MASK 0x1f
248 #define VPE_EDI_LUT4_SHIFT 0
249 #define VPE_EDI_LUT5_MASK 0x1f
251 #define VPE_EDI_LUT6_MASK 0x1f
253 #define VPE_EDI_LUT7_MASK 0x1f
256 #define VPE_DEI_EDI_LUT_R3 0x061c
257 #define VPE_EDI_LUT8_MASK 0x1f
258 #define VPE_EDI_LUT8_SHIFT 0
259 #define VPE_EDI_LUT9_MASK 0x1f
261 #define VPE_EDI_LUT10_MASK 0x1f
263 #define VPE_EDI_LUT11_MASK 0x1f
266 #define VPE_DEI_FMD_WINDOW_R0 0x0620
267 #define VPE_FMD_WINDOW_MINX_MASK 0x07ff
268 #define VPE_FMD_WINDOW_MINX_SHIFT 0
269 #define VPE_FMD_WINDOW_MAXX_MASK 0x07ff
273 #define VPE_DEI_FMD_WINDOW_R1 0x0624
274 #define VPE_FMD_WINDOW_MINY_MASK 0x07ff
275 #define VPE_FMD_WINDOW_MINY_SHIFT 0
276 #define VPE_FMD_WINDOW_MAXY_MASK 0x07ff
279 #define VPE_DEI_FMD_CONTROL_R0 0x0628
280 #define VPE_FMD_ENABLE BIT(0)
284 #define VPE_FMD_CAF_FIELD_THR_MASK 0xff
286 #define VPE_FMD_CAF_LINE_THR_MASK 0xff
289 #define VPE_DEI_FMD_CONTROL_R1 0x062c
290 #define VPE_FMD_CAF_THR_MASK 0x000fffff
291 #define VPE_FMD_CAF_THR_SHIFT 0
293 #define VPE_DEI_FMD_STATUS_R0 0x0630
294 #define VPE_FMD_CAF_MASK 0x000fffff
295 #define VPE_FMD_CAF_SHIFT 0
298 #define VPE_DEI_FMD_STATUS_R1 0x0634
299 #define VPE_FMD_FIELD_DIFF_MASK 0x0fffffff
300 #define VPE_FMD_FIELD_DIFF_SHIFT 0
302 #define VPE_DEI_FMD_STATUS_R2 0x0638
303 #define VPE_FMD_FRAME_DIFF_MASK 0x000fffff
304 #define VPE_FMD_FRAME_DIFF_SHIFT 0