Lines Matching +full:0 +full:x7f
20 #define DEINTERLACE_MOD_ENABLE 0x00
21 #define DEINTERLACE_MOD_ENABLE_EN BIT(0)
23 #define DEINTERLACE_FRM_CTRL 0x04
24 #define DEINTERLACE_FRM_CTRL_REG_READY BIT(0)
30 #define DEINTERLACE_BYPASS 0x08
33 #define DEINTERLACE_AGTH_SEL 0x0c
36 #define DEINTERLACE_LINT_CTRL 0x10
37 #define DEINTERLACE_TRD_PRELUMA 0x1c
38 #define DEINTERLACE_BUF_ADDR0 0x20
39 #define DEINTERLACE_BUF_ADDR1 0x24
40 #define DEINTERLACE_BUF_ADDR2 0x28
42 #define DEINTERLACE_FIELD_CTRL 0x2c
43 #define DEINTERLACE_FIELD_CTRL_FIELD_CNT(v) ((v) & 0xff)
44 #define DEINTERLACE_FIELD_CTRL_FIELD_CNT_MSK (0xff)
46 #define DEINTERLACE_TB_OFFSET0 0x30
47 #define DEINTERLACE_TB_OFFSET1 0x34
48 #define DEINTERLACE_TB_OFFSET2 0x38
49 #define DEINTERLACE_TRD_PRECHROMA 0x3c
50 #define DEINTERLACE_LINE_STRIDE0 0x40
51 #define DEINTERLACE_LINE_STRIDE1 0x44
52 #define DEINTERLACE_LINE_STRIDE2 0x48
54 #define DEINTERLACE_IN_FMT 0x4c
59 #define DEINTERLACE_WB_ADDR0 0x50
60 #define DEINTERLACE_WB_ADDR1 0x54
61 #define DEINTERLACE_WB_ADDR2 0x58
63 #define DEINTERLACE_OUT_FMT 0x5c
64 #define DEINTERLACE_OUT_FMT_FMT(v) ((v) & 0xf)
67 #define DEINTERLACE_INT_ENABLE 0x60
70 #define DEINTERLACE_INT_STATUS 0x64
73 #define DEINTERLACE_STATUS 0x68
77 #define DEINTERLACE_CSC_COEF 0x70 /* 12 registers */
79 #define DEINTERLACE_CTRL 0xa0
80 #define DEINTERLACE_CTRL_EN BIT(0)
82 #define DEINTERLACE_CTRL_MODE_PASSTROUGH (0 << 16)
89 #define DEINTERLACE_DIAG_INTP 0xa4
90 #define DEINTERLACE_DIAG_INTP_TH0(v) ((v) & 0x7f)
91 #define DEINTERLACE_DIAG_INTP_TH0_MSK (0x7f)
92 #define DEINTERLACE_DIAG_INTP_TH1(v) (((v) & 0x7f) << 8)
93 #define DEINTERLACE_DIAG_INTP_TH1_MSK (0x7f << 8)
94 #define DEINTERLACE_DIAG_INTP_TH3(v) (((v) & 0xff) << 24)
95 #define DEINTERLACE_DIAG_INTP_TH3_MSK (0xff << 24)
97 #define DEINTERLACE_TEMP_DIFF 0xa8
98 #define DEINTERLACE_TEMP_DIFF_SAD_CENTRAL_TH(v) ((v) & 0x7f)
99 #define DEINTERLACE_TEMP_DIFF_SAD_CENTRAL_TH_MSK (0x7f)
100 #define DEINTERLACE_TEMP_DIFF_AMBIGUITY_TH(v) (((v) & 0x7f) << 8)
101 #define DEINTERLACE_TEMP_DIFF_AMBIGUITY_TH_MSK (0x7f << 8)
102 #define DEINTERLACE_TEMP_DIFF_DIRECT_DITHER_TH(v) (((v) & 0x7ff) << 16)
103 #define DEINTERLACE_TEMP_DIFF_DIRECT_DITHER_TH_MSK (0x7ff << 16)
105 #define DEINTERLACE_LUMA_TH 0xac
106 #define DEINTERLACE_LUMA_TH_MIN_LUMA(v) ((v) & 0xff)
107 #define DEINTERLACE_LUMA_TH_MIN_LUMA_MSK (0xff)
108 #define DEINTERLACE_LUMA_TH_MAX_LUMA(v) (((v) & 0xff) << 8)
109 #define DEINTERLACE_LUMA_TH_MAX_LUMA_MSK (0xff << 8)
110 #define DEINTERLACE_LUMA_TH_AVG_LUMA_SHIFT(v) (((v) & 0xff) << 16)
111 #define DEINTERLACE_LUMA_TH_AVG_LUMA_SHIFT_MSK (0xff << 16)
115 #define DEINTERLACE_SPAT_COMP 0xb0
116 #define DEINTERLACE_SPAT_COMP_TH2(v) ((v) & 0xff)
117 #define DEINTERLACE_SPAT_COMP_TH2_MSK (0xff)
118 #define DEINTERLACE_SPAT_COMP_TH3(v) (((v) & 0xff) << 16)
119 #define DEINTERLACE_SPAT_COMP_TH3_MSK (0xff << 16)
121 #define DEINTERLACE_CHROMA_DIFF 0xb4
122 #define DEINTERLACE_CHROMA_DIFF_TH(v) ((v) & 0xff)
123 #define DEINTERLACE_CHROMA_DIFF_TH_MSK (0xff)
124 #define DEINTERLACE_CHROMA_DIFF_LUMA(v) (((v) & 0x3f) << 16)
125 #define DEINTERLACE_CHROMA_DIFF_LUMA_MSK (0x3f << 16)
126 #define DEINTERLACE_CHROMA_DIFF_CHROMA(v) (((v) & 0x3f) << 24)
127 #define DEINTERLACE_CHROMA_DIFF_CHROMA_MSK (0x3f << 24)
129 #define DEINTERLACE_PRELUMA 0xb8
130 #define DEINTERLACE_PRECHROMA 0xbc
131 #define DEINTERLACE_TILE_FLAG0 0xc0
132 #define DEINTERLACE_TILE_FLAG1 0xc4
133 #define DEINTERLACE_FLAG_LINE_STRIDE 0xc8
134 #define DEINTERLACE_FLAG_SEQ 0xcc
136 #define DEINTERLACE_WB_LINE_STRIDE_CTRL 0xd0
137 #define DEINTERLACE_WB_LINE_STRIDE_CTRL_EN BIT(0)
139 #define DEINTERLACE_WB_LINE_STRIDE0 0xd4
140 #define DEINTERLACE_WB_LINE_STRIDE1 0xd8
141 #define DEINTERLACE_WB_LINE_STRIDE2 0xdc
142 #define DEINTERLACE_TRD_CTRL 0xe0
143 #define DEINTERLACE_TRD_BUF_ADDR0 0xe4
144 #define DEINTERLACE_TRD_BUF_ADDR1 0xe8
145 #define DEINTERLACE_TRD_BUF_ADDR2 0xec
146 #define DEINTERLACE_TRD_TB_OFF0 0xf0
147 #define DEINTERLACE_TRD_TB_OFF1 0xf4
148 #define DEINTERLACE_TRD_TB_OFF2 0xf8
149 #define DEINTERLACE_TRD_WB_STRIDE 0xfc
150 #define DEINTERLACE_CH0_IN_SIZE 0x100
151 #define DEINTERLACE_CH0_OUT_SIZE 0x104
152 #define DEINTERLACE_CH0_HORZ_FACT 0x108
153 #define DEINTERLACE_CH0_VERT_FACT 0x10c
154 #define DEINTERLACE_CH0_HORZ_PHASE 0x110
155 #define DEINTERLACE_CH0_VERT_PHASE0 0x114
156 #define DEINTERLACE_CH0_VERT_PHASE1 0x118
157 #define DEINTERLACE_CH0_HORZ_TAP0 0x120
158 #define DEINTERLACE_CH0_HORZ_TAP1 0x124
159 #define DEINTERLACE_CH0_VERT_TAP 0x128
160 #define DEINTERLACE_CH1_IN_SIZE 0x200
161 #define DEINTERLACE_CH1_OUT_SIZE 0x204
162 #define DEINTERLACE_CH1_HORZ_FACT 0x208
163 #define DEINTERLACE_CH1_VERT_FACT 0x20c
164 #define DEINTERLACE_CH1_HORZ_PHASE 0x210
165 #define DEINTERLACE_CH1_VERT_PHASE0 0x214
166 #define DEINTERLACE_CH1_VERT_PHASE1 0x218
167 #define DEINTERLACE_CH1_HORZ_TAP0 0x220
168 #define DEINTERLACE_CH1_HORZ_TAP1 0x224
169 #define DEINTERLACE_CH1_VERT_TAP 0x228
170 #define DEINTERLACE_CH0_HORZ_COEF0 0x400 /* 32 registers */
171 #define DEINTERLACE_CH0_HORZ_COEF1 0x480 /* 32 registers */
172 #define DEINTERLACE_CH0_VERT_COEF 0x500 /* 32 registers */
173 #define DEINTERLACE_CH1_HORZ_COEF0 0x600 /* 32 registers */
174 #define DEINTERLACE_CH1_HORZ_COEF1 0x680 /* 32 registers */
175 #define DEINTERLACE_CH1_VERT_COEF 0x700 /* 32 registers */
176 #define DEINTERLACE_CH3_HORZ_COEF0 0x800 /* 32 registers */
177 #define DEINTERLACE_CH3_HORZ_COEF1 0x880 /* 32 registers */
178 #define DEINTERLACE_CH3_VERT_COEF 0x900 /* 32 registers */
191 #define DEINTERLACE_PS_UVUV 0
194 #define DEINTERLACE_IDENTITY_COEF 0x4000