Lines Matching +full:0 +full:x93
35 #define R_BYPASS 0x05 /* Bypass DSP */
36 #define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */
37 #define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */
38 #define QS 0x44 /* Quantization Scale Factor */
39 #define CTRLI 0x50
40 #define CTRLI_LP_DP 0x80
41 #define CTRLI_ROUND 0x40
42 #define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3)
43 #define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0)
44 #define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */
45 #define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
46 #define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */
47 #define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
48 #define XOFFL 0x53 /* OFFSET_X[7:0] */
49 #define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
50 #define YOFFL 0x54 /* OFFSET_Y[7:0] */
51 #define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
52 #define VHYX 0x55 /* Offset and size completion */
53 #define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7)
54 #define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3)
55 #define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4)
56 #define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0)
57 #define DPRP 0x56
58 #define TEST 0x57 /* Horizontal size completion */
59 #define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7)
60 #define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */
61 #define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0)
62 #define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */
63 #define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0)
64 #define ZMHH 0x5C /* Zoom: Speed and H&W completion */
65 #define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4)
66 #define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2)
67 #define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0)
68 #define BPADDR 0x7C /* SDE Indirect Register Access: Address */
69 #define BPDATA 0x7D /* SDE Indirect Register Access: Data */
70 #define CTRL2 0x86 /* DSP Module enable 2 */
71 #define CTRL2_DCW_EN 0x20
72 #define CTRL2_SDE_EN 0x10
73 #define CTRL2_UV_ADJ_EN 0x08
74 #define CTRL2_UV_AVG_EN 0x04
75 #define CTRL2_CMX_EN 0x01
76 #define CTRL3 0x87 /* DSP Module enable 3 */
77 #define CTRL3_BPC_EN 0x80
78 #define CTRL3_WPC_EN 0x40
79 #define SIZEL 0x8C /* Image Size Completion */
80 #define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6)
81 #define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3)
82 #define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0)
83 #define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */
84 #define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
85 #define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */
86 #define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
87 #define CTRL0 0xC2 /* DSP Module enable 0 */
88 #define CTRL0_AEC_EN 0x80
89 #define CTRL0_AEC_SEL 0x40
90 #define CTRL0_STAT_SEL 0x20
91 #define CTRL0_VFIRST 0x10
92 #define CTRL0_YUV422 0x08
93 #define CTRL0_YUV_EN 0x04
94 #define CTRL0_RGB_EN 0x02
95 #define CTRL0_RAW_EN 0x01
96 #define CTRL1 0xC3 /* DSP Module enable 1 */
97 #define CTRL1_CIP 0x80
98 #define CTRL1_DMY 0x40
99 #define CTRL1_RAW_GMA 0x20
100 #define CTRL1_DG 0x10
101 #define CTRL1_AWB 0x08
102 #define CTRL1_AWB_GAIN 0x04
103 #define CTRL1_LENC 0x02
104 #define CTRL1_PRE 0x01
105 /* REG 0xC7 (unknown name): affects Auto White Balance (AWB)
106 * AWB_OFF 0x40
107 * AWB_SIMPLE 0x10
108 * AWB_ON 0x00 (Advanced AWB ?) */
109 #define R_DVP_SP 0xD3 /* DVP output speed control */
110 #define R_DVP_SP_AUTO_MODE 0x80
111 #define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0);
112 * = sysclk (48)/(2*[6:0]) (RAW);*/
113 #define IMAGE_MODE 0xDA /* Image Output Format Select */
114 #define IMAGE_MODE_Y8_DVP_EN 0x40
115 #define IMAGE_MODE_JPEG_EN 0x10
116 #define IMAGE_MODE_YUV422 0x00
117 #define IMAGE_MODE_RAW10 0x04 /* (DVP) */
118 #define IMAGE_MODE_RGB565 0x08
119 #define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output
120 * mode (0 for HREF is same as sensor) */
121 #define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP
122 * 1: Low byte first UYVY (C2[4] =0)
124 * 0: High byte first YUYV (C2[4]=0)
126 #define RESET 0xE0 /* Reset */
127 #define RESET_MICROC 0x40
128 #define RESET_SCCB 0x20
129 #define RESET_JPEG 0x10
130 #define RESET_DVP 0x04
131 #define RESET_IPU 0x02
132 #define RESET_CIF 0x01
133 #define REGED 0xED /* Register ED */
134 #define REGED_CLK_OUT_DIS 0x10
135 #define MS_SP 0xF0 /* SCCB Master Speed */
136 #define SS_ID 0xF7 /* SCCB Slave ID */
137 #define SS_CTRL 0xF8 /* SCCB Slave Control */
138 #define SS_CTRL_ADD_AUTO_INC 0x20
139 #define SS_CTRL_EN 0x08
140 #define SS_CTRL_DELAY_CLK 0x04
141 #define SS_CTRL_ACC_EN 0x02
142 #define SS_CTRL_SEN_PASS_THR 0x01
143 #define MC_BIST 0xF9 /* Microcontroller misc register */
144 #define MC_BIST_RESET 0x80 /* Microcontroller Reset */
145 #define MC_BIST_BOOT_ROM_SEL 0x40
146 #define MC_BIST_12KB_SEL 0x20
147 #define MC_BIST_12KB_MASK 0x30
148 #define MC_BIST_512KB_SEL 0x08
149 #define MC_BIST_512KB_MASK 0x0C
150 #define MC_BIST_BUSY_BIT_R 0x02
151 #define MC_BIST_MC_RES_ONE_SH_W 0x02
152 #define MC_BIST_LAUNCH 0x01
153 #define BANK_SEL 0xFF /* Register Bank Select */
154 #define BANK_SEL_DSP 0x00
155 #define BANK_SEL_SENS 0x01
161 #define GAIN 0x00 /* AGC - Gain control gain setting */
162 #define COM1 0x03 /* Common control 1 */
163 #define COM1_1_DUMMY_FR 0x40
164 #define COM1_3_DUMMY_FR 0x80
165 #define COM1_7_DUMMY_FR 0xC0
166 #define COM1_VWIN_LSB_UXGA 0x0F
167 #define COM1_VWIN_LSB_SVGA 0x0A
168 #define COM1_VWIN_LSB_CIF 0x06
169 #define REG04 0x04 /* Register 04 */
170 #define REG04_DEF 0x20 /* Always set */
171 #define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */
172 #define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */
173 #define REG04_VREF_EN 0x10
174 #define REG04_HREF_EN 0x08
175 #define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0)
176 #define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */
177 #define COM2 0x09 /* Common control 2 */
178 #define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */
180 #define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */
181 #define PID 0x0A /* Product ID Number MSB */
182 #define VER 0x0B /* Product ID Number LSB */
183 #define COM3 0x0C /* Common control 3 */
184 #define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */
185 #define COM3_BAND_AUTO 0x02 /* Auto Banding */
186 #define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the
188 #define AEC 0x10 /* AEC[9:2] Exposure Value */
189 #define CLKRC 0x11 /* Internal clock */
190 #define CLKRC_EN 0x80
191 #define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */
192 #define COM7 0x12 /* Common control 7 */
193 #define COM7_SRST 0x80 /* Initiates system reset. All registers are
196 #define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */
197 #define COM7_RES_SVGA 0x40 /* SVGA */
198 #define COM7_RES_CIF 0x20 /* CIF */
199 #define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */
200 #define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */
201 #define COM8 0x13 /* Common control 8 */
202 #define COM8_DEF 0xC0
203 #define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */
204 #define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */
205 #define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */
206 #define COM9 0x14 /* Common control 9
208 #define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */
209 #define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */
210 #define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */
211 #define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */
212 #define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */
213 #define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */
214 #define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */
215 #define COM10 0x15 /* Common control 10 */
216 #define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */
217 #define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of
220 * 0 otherwise. */
221 #define COM10_HREF_INV 0x08 /* Invert HREF polarity:
223 #define COM10_VSINC_INV 0x02 /* Invert VSYNC polarity */
224 #define HSTART 0x17 /* Horizontal Window start MSB 8 bit */
225 #define HEND 0x18 /* Horizontal Window end MSB 8 bit */
226 #define VSTART 0x19 /* Vertical Window start MSB 8 bit */
227 #define VEND 0x1A /* Vertical Window end MSB 8 bit */
228 #define MIDH 0x1C /* Manufacturer ID byte - high */
229 #define MIDL 0x1D /* Manufacturer ID byte - low */
230 #define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */
231 #define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */
232 #define VV 0x26 /* AGC/AEC Fast mode operating region */
233 #define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4)
234 #define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0)
235 #define REG2A 0x2A /* Dummy pixel insert MSB */
236 #define FRARL 0x2B /* Dummy pixel insert LSB */
237 #define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */
238 #define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */
239 #define YAVG 0x2F /* Y/G Channel Average value */
240 #define REG32 0x32 /* Common Control 32 */
241 #define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */
242 #define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */
243 #define ARCOM2 0x34 /* Zoom: Horizontal start point */
244 #define REG45 0x45 /* Register 45 */
245 #define FLL 0x46 /* Frame Length Adjustment LSBs */
246 #define FLH 0x47 /* Frame Length Adjustment MSBs */
247 #define COM19 0x48 /* Zoom: Vertical start point */
248 #define ZOOMS 0x49 /* Zoom: Vertical start point */
249 #define COM22 0x4B /* Flash light control */
250 #define COM25 0x4E /* For Banding operations */
251 #define COM25_50HZ_BANDING_AEC_MSBS_MASK 0xC0 /* 50Hz Bd. AEC 2 MSBs */
252 #define COM25_60HZ_BANDING_AEC_MSBS_MASK 0x30 /* 60Hz Bd. AEC 2 MSBs */
253 #define COM25_50HZ_BANDING_AEC_MSBS_SET(x) VAL_SET(x, 0x3, 8, 6)
254 #define COM25_60HZ_BANDING_AEC_MSBS_SET(x) VAL_SET(x, 0x3, 8, 4)
255 #define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */
256 #define BD50_50HZ_BANDING_AEC_LSBS_SET(x) VAL_SET(x, 0xFF, 0, 0)
257 #define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */
258 #define BD60_60HZ_BANDING_AEC_LSBS_SET(x) VAL_SET(x, 0xFF, 0, 0)
259 #define REG5A 0x5A /* 50/60Hz Banding Maximum AEC Step */
260 #define BD50_MAX_AEC_STEP_MASK 0xF0 /* 50Hz Banding Max. AEC Step */
261 #define BD60_MAX_AEC_STEP_MASK 0x0F /* 60Hz Banding Max. AEC Step */
262 #define BD50_MAX_AEC_STEP_SET(x) VAL_SET((x - 1), 0x0F, 0, 4)
263 #define BD60_MAX_AEC_STEP_SET(x) VAL_SET((x - 1), 0x0F, 0, 0)
264 #define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */
265 #define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */
266 #define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */
267 #define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */
268 #define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */
269 #define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */
274 #define MANUFACTURER_ID 0x7FA2
275 #define PID_OV2640 0x2642
276 #define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF))
316 #define ENDMARKER { 0xff, 0xff }
320 { 0x2c, 0xff },
321 { 0x2e, 0xdf },
323 { 0x3c, 0x32 },
328 { COM9, COM9_AGC_GAIN_8x | 0x08},
329 { 0x2c, 0x0c },
330 { 0x33, 0x78 },
331 { 0x3a, 0x33 },
332 { 0x3b, 0xfb },
333 { 0x3e, 0x00 },
334 { 0x43, 0x11 },
335 { 0x16, 0x10 },
336 { 0x39, 0x02 },
337 { 0x35, 0x88 },
338 { 0x22, 0x0a },
339 { 0x37, 0x40 },
340 { 0x23, 0x00 },
341 { ARCOM2, 0xa0 },
342 { 0x06, 0x02 },
343 { 0x06, 0x88 },
344 { 0x07, 0xc0 },
345 { 0x0d, 0xb7 },
346 { 0x0e, 0x01 },
347 { 0x4c, 0x00 },
348 { 0x4a, 0x81 },
349 { 0x21, 0x99 },
350 { AEW, 0x40 },
351 { AEB, 0x38 },
352 { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) },
353 { 0x5c, 0x00 },
354 { 0x63, 0x00 },
355 { FLL, 0x22 },
356 { COM3, 0x38 | COM3_BAND_AUTO },
357 { REG5D, 0x55 },
358 { REG5E, 0x7d },
359 { REG5F, 0x7d },
360 { REG60, 0x55 },
361 { HISTO_LOW, 0x70 },
362 { HISTO_HIGH, 0x80 },
363 { 0x7c, 0x05 },
364 { 0x20, 0x80 },
365 { 0x28, 0x30 },
366 { 0x6c, 0x00 },
367 { 0x6d, 0x80 },
368 { 0x6e, 0x00 },
369 { 0x70, 0x02 },
370 { 0x71, 0x94 },
371 { 0x73, 0xc1 },
372 { 0x3d, 0x34 },
375 | BD60_MAX_AEC_STEP_SET(8) }, /* 0x57 */
376 { COM25, COM25_50HZ_BANDING_AEC_MSBS_SET(0x0bb)
377 | COM25_60HZ_BANDING_AEC_MSBS_SET(0x09c) }, /* 0x00 */
378 { BD50, BD50_50HZ_BANDING_AEC_LSBS_SET(0x0bb) }, /* 0xbb */
379 { BD60, BD60_60HZ_BANDING_AEC_LSBS_SET(0x09c) }, /* 0x9c */
381 { 0xe5, 0x7f },
383 { 0x41, 0x24 },
385 { 0x76, 0xff },
386 { 0x33, 0xa0 },
387 { 0x42, 0x20 },
388 { 0x43, 0x18 },
389 { 0x4c, 0x00 },
390 { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 },
391 { 0x88, 0x3f },
392 { 0xd7, 0x03 },
393 { 0xd9, 0x10 },
394 { R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x2 },
395 { 0xc8, 0x08 },
396 { 0xc9, 0x80 },
397 { BPADDR, 0x00 },
398 { BPDATA, 0x00 },
399 { BPADDR, 0x03 },
400 { BPDATA, 0x48 },
401 { BPDATA, 0x48 },
402 { BPADDR, 0x08 },
403 { BPDATA, 0x20 },
404 { BPDATA, 0x10 },
405 { BPDATA, 0x0e },
406 { 0x90, 0x00 },
407 { 0x91, 0x0e },
408 { 0x91, 0x1a },
409 { 0x91, 0x31 },
410 { 0x91, 0x5a },
411 { 0x91, 0x69 },
412 { 0x91, 0x75 },
413 { 0x91, 0x7e },
414 { 0x91, 0x88 },
415 { 0x91, 0x8f },
416 { 0x91, 0x96 },
417 { 0x91, 0xa3 },
418 { 0x91, 0xaf },
419 { 0x91, 0xc4 },
420 { 0x91, 0xd7 },
421 { 0x91, 0xe8 },
422 { 0x91, 0x20 },
423 { 0x92, 0x00 },
424 { 0x93, 0x06 },
425 { 0x93, 0xe3 },
426 { 0x93, 0x03 },
427 { 0x93, 0x03 },
428 { 0x93, 0x00 },
429 { 0x93, 0x02 },
430 { 0x93, 0x00 },
431 { 0x93, 0x00 },
432 { 0x93, 0x00 },
433 { 0x93, 0x00 },
434 { 0x93, 0x00 },
435 { 0x93, 0x00 },
436 { 0x93, 0x00 },
437 { 0x96, 0x00 },
438 { 0x97, 0x08 },
439 { 0x97, 0x19 },
440 { 0x97, 0x02 },
441 { 0x97, 0x0c },
442 { 0x97, 0x24 },
443 { 0x97, 0x30 },
444 { 0x97, 0x28 },
445 { 0x97, 0x26 },
446 { 0x97, 0x02 },
447 { 0x97, 0x98 },
448 { 0x97, 0x80 },
449 { 0x97, 0x00 },
450 { 0x97, 0x00 },
451 { 0xa4, 0x00 },
452 { 0xa8, 0x00 },
453 { 0xc5, 0x11 },
454 { 0xc6, 0x51 },
455 { 0xbf, 0x80 },
456 { 0xc7, 0x10 }, /* simple AWB */
457 { 0xb6, 0x66 },
458 { 0xb8, 0xA5 },
459 { 0xb7, 0x64 },
460 { 0xb9, 0x7C },
461 { 0xb3, 0xaf },
462 { 0xb4, 0x97 },
463 { 0xb5, 0xFF },
464 { 0xb0, 0xC5 },
465 { 0xb1, 0x94 },
466 { 0xb2, 0x0f },
467 { 0xc4, 0x5c },
468 { 0xa6, 0x00 },
469 { 0xa7, 0x20 },
470 { 0xa7, 0xd8 },
471 { 0xa7, 0x1b },
472 { 0xa7, 0x31 },
473 { 0xa7, 0x00 },
474 { 0xa7, 0x18 },
475 { 0xa7, 0x20 },
476 { 0xa7, 0xd8 },
477 { 0xa7, 0x19 },
478 { 0xa7, 0x31 },
479 { 0xa7, 0x00 },
480 { 0xa7, 0x18 },
481 { 0xa7, 0x20 },
482 { 0xa7, 0xd8 },
483 { 0xa7, 0x19 },
484 { 0xa7, 0x31 },
485 { 0xa7, 0x00 },
486 { 0xa7, 0x18 },
487 { 0x7f, 0x00 },
488 { 0xe5, 0x1f },
489 { 0xe1, 0x77 },
490 { 0xdd, 0x7f },
512 { XOFFL, XOFFL_SET(0) },
513 { YOFFL, YOFFL_SET(0) },
515 VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)},
527 { RESET, 0x00}
545 PER_SIZE_REG_SEQ(VGA_WIDTH, VGA_HEIGHT, 0, 0, 2),
555 PER_SIZE_REG_SEQ(XGA_WIDTH, XGA_HEIGHT, 0, 0, 2),
556 { CTRLI, 0x00},
561 PER_SIZE_REG_SEQ(SXGA_WIDTH, SXGA_HEIGHT, 0, 0, 2),
562 { CTRLI, 0x00},
568 PER_SIZE_REG_SEQ(UXGA_WIDTH, UXGA_HEIGHT, 0, 0, 0),
569 { CTRLI, 0x00},
570 { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE },
599 { 0xd7, 0x03 },
600 { 0x33, 0xa0 },
601 { 0xe5, 0x1f },
602 { 0xe1, 0x67 },
603 { RESET, 0x00 },
610 { 0xd7, 0x01 },
611 { 0x33, 0xa0 },
612 { 0xe1, 0x67 },
613 { RESET, 0x00 },
620 { 0xd7, 0x03 },
621 { RESET, 0x00 },
628 { 0xd7, 0x03 },
629 { RESET, 0x00 },
657 while ((vals->reg_num != 0xff) || (vals->value != 0xff)) { in ov2640_write_array()
660 dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x", in ov2640_write_array()
663 if (ret < 0) in ov2640_write_array()
667 return 0; in ov2640_write_array()
674 if (val < 0) in ov2640_mask_set()
680 dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val); in ov2640_mask_set()
729 return 0; in ov2640_s_ctrl()
732 if (ret < 0) in ov2640_s_ctrl()
737 val = ctrl->val ? REG04_VFLIP_IMG | REG04_VREF_EN : 0x00; in ov2640_s_ctrl()
742 val = ctrl->val ? REG04_HFLIP_IMG : 0x00; in ov2640_s_ctrl()
745 val = ctrl->val ? COM7_COLOR_BAR_TEST : 0x00; in ov2640_s_ctrl()
760 if (reg->reg > 0xff) in ov2640_g_register()
764 if (ret < 0) in ov2640_g_register()
769 return 0; in ov2640_g_register()
777 if (reg->reg > 0xff || in ov2640_s_register()
778 reg->val > 0xff) in ov2640_s_register()
794 gpiod_set_value(priv->resetb_gpio, 0); in ov2640_set_power()
807 * If the power count is modified from 0 to != 0 or from != 0 to 0, in ov2640_s_power()
813 WARN_ON(priv->power_count < 0); in ov2640_s_power()
816 return 0; in ov2640_s_power()
824 for (i = 0; i < ARRAY_SIZE(ov2640_supported_win_sizes); i++) { in ov2640_select_win()
874 if (ret < 0) in ov2640_set_params()
880 if (ret < 0) in ov2640_set_params()
885 if (ret < 0) in ov2640_set_params()
891 if (ret < 0) in ov2640_set_params()
896 if (ret < 0) in ov2640_set_params()
899 || (code == MEDIA_BUS_FMT_VYUY8_2X8) ? CTRL0_VFIRST : 0x00; in ov2640_set_params()
901 if (ret < 0) in ov2640_set_params()
904 return 0; in ov2640_set_params()
926 mf = v4l2_subdev_get_try_format(sd, sd_state, 0); in ov2640_get_fmt()
928 return 0; in ov2640_get_fmt()
943 return 0; in ov2640_get_fmt()
954 int ret = 0; in ov2640_set_fmt()
1010 v4l2_subdev_get_try_format(sd, sd_state, 0); in ov2640_init_cfg()
1023 return 0; in ov2640_init_cfg()
1034 return 0; in ov2640_enum_mbus_code()
1047 sel->r.left = 0; in ov2640_get_selection()
1048 sel->r.top = 0; in ov2640_get_selection()
1051 return 0; in ov2640_get_selection()
1061 int ret = 0; in ov2640_s_stream()
1087 if (ret < 0) in ov2640_video_probe()
1111 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n", in ov2640_video_probe()
1115 ov2640_s_power(&priv->subdev, 0); in ov2640_video_probe()
1185 return 0; in ov2640_probe_dt()
1230 V4L2_CID_VFLIP, 0, 1, 1, 0); in ov2640_probe()
1232 V4L2_CID_HFLIP, 0, 1, 1, 0); in ov2640_probe()
1235 ARRAY_SIZE(ov2640_test_pattern_menu) - 1, 0, 0, in ov2640_probe()
1246 if (ret < 0) in ov2640_probe()
1251 if (ret < 0) in ov2640_probe()
1255 if (ret < 0) in ov2640_probe()
1260 return 0; in ov2640_probe()
1285 { "ov2640", 0 },