347 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)  in io_write()  function
356 	return io_write(sd, reg, (io_read(sd, reg) & mask) | val);  in io_write_and_or()
362 	return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);  in io_write_clr_set()
911 		io_write(sd, reg->reg & 0xff, val);  in adv7842_s_register()
977 		io_write(sd, 0x00, predef_vid_timings[i].vid_std);  in find_and_set_predefined_video_timings()
979 		io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);  in find_and_set_predefined_video_timings()
995 	io_write(sd, 0x16, 0x43);  in configure_predefined_video_timings()
996 	io_write(sd, 0x17, 0x5a);  in configure_predefined_video_timings()
1062 		io_write(sd, 0x00, 0x07); /* video std */  in configure_custom_video_timings()
1063 		io_write(sd, 0x01, 0x02); /* prim mode */  in configure_custom_video_timings()
1090 		io_write(sd, 0x00, 0x02); /* video std */  in configure_custom_video_timings()
1091 		io_write(sd, 0x01, 0x06); /* prim mode */  in configure_custom_video_timings()
1712 		io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */  in enable_input()
1716 		io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */  in enable_input()
1730 	io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */  in disable_input()
1790 		io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */  in select_input()
1791 		io_write(sd, 0x01, 0); /* prim mode */  in select_input()
1798 		io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */  in select_input()
1838 		io_write(sd, 0x00, vid_std_select); /* video std */  in select_input()
1839 		io_write(sd, 0x01, 0x02); /* prim mode */  in select_input()
1878 		io_write(sd, 0x00, vid_std_select); /* video std */  in select_input()
1879 		io_write(sd, 0x01, 5); /* prim mode */  in select_input()
2053 	io_write(sd, 0x03, state->format->op_format_sel |  in adv7842_setup_format()
2136 		io_write(sd, 0x46, 0x9c);  in adv7842_irq_enable()
2138 		io_write(sd, 0x5a, 0x10);  in adv7842_irq_enable()
2140 		io_write(sd, 0x73, 0x03);  in adv7842_irq_enable()
2142 		io_write(sd, 0x78, 0x03);  in adv7842_irq_enable()
2144 		io_write(sd, 0xa0, 0x09);  in adv7842_irq_enable()
2146 		io_write(sd, 0x69, 0x08);  in adv7842_irq_enable()
2148 		io_write(sd, 0x46, 0x0);  in adv7842_irq_enable()
2149 		io_write(sd, 0x5a, 0x0);  in adv7842_irq_enable()
2150 		io_write(sd, 0x73, 0x0);  in adv7842_irq_enable()
2151 		io_write(sd, 0x78, 0x0);  in adv7842_irq_enable()
2152 		io_write(sd, 0xa0, 0x0);  in adv7842_irq_enable()
2153 		io_write(sd, 0x69, 0x0);  in adv7842_irq_enable()
2231 	io_write(sd, 0x94, cec_irq);  in adv7842_cec_isr()
2376 		io_write(sd, 0x44, irq_status[0]);  in adv7842_isr()
2378 		io_write(sd, 0x58, irq_status[1]);  in adv7842_isr()
2380 		io_write(sd, 0x71, irq_status[2]);  in adv7842_isr()
2382 		io_write(sd, 0x76, irq_status[3]);  in adv7842_isr()
2384 		io_write(sd, 0x9e, irq_status[4]);  in adv7842_isr()
2386 		io_write(sd, 0x67, irq_status[5]);  in adv7842_isr()
3003 	io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */  in adv7842_core_init()
3004 	io_write(sd, 0x15, 0x80);   /* Power up pads */  in adv7842_core_init()
3007 	io_write(sd, 0x02, 0xf0 | pdata->alt_gamma << 3);  in adv7842_core_init()
3034 	io_write(sd, 0x06, 0xa6);   /* positive VS and HS and DE */  in adv7842_core_init()
3086 	io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);  in adv7842_core_init()
3087 	io_write(sd, 0x33, 0x40);  in adv7842_core_init()
3090 	io_write(sd, 0x40, 0xf2); /* Configure INT1 */  in adv7842_core_init()
3112 	io_write(sd, 0x00, 0x01);  /* Program SDP 4x1 */  in adv7842_ddr_ram_test()
3113 	io_write(sd, 0x01, 0x00);  /* Program SDP mode */  in adv7842_ddr_ram_test()
3120 	io_write(sd, 0x0C, 0x40);  /* Power up ADV7844 */  in adv7842_ddr_ram_test()
3121 	io_write(sd, 0x15, 0xBA);  /* Enable outputs */  in adv7842_ddr_ram_test()
3123 	io_write(sd, 0xFF, 0x04);  /* Reset memory controller */  in adv7842_ddr_ram_test()
3170 	io_write(sd, 0xf1, pdata->i2c_sdp << 1);  in adv7842_rewrite_i2c_addresses()
3171 	io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);  in adv7842_rewrite_i2c_addresses()
3172 	io_write(sd, 0xf3, pdata->i2c_avlink << 1);  in adv7842_rewrite_i2c_addresses()
3173 	io_write(sd, 0xf4, pdata->i2c_cec << 1);  in adv7842_rewrite_i2c_addresses()
3174 	io_write(sd, 0xf5, pdata->i2c_infoframe << 1);  in adv7842_rewrite_i2c_addresses()
3176 	io_write(sd, 0xf8, pdata->i2c_afe << 1);  in adv7842_rewrite_i2c_addresses()
3177 	io_write(sd, 0xf9, pdata->i2c_repeater << 1);  in adv7842_rewrite_i2c_addresses()
3178 	io_write(sd, 0xfa, pdata->i2c_edid << 1);  in adv7842_rewrite_i2c_addresses()
3179 	io_write(sd, 0xfb, pdata->i2c_hdmi << 1);  in adv7842_rewrite_i2c_addresses()
3181 	io_write(sd, 0xfd, pdata->i2c_cp << 1);  in adv7842_rewrite_i2c_addresses()
3182 	io_write(sd, 0xfe, pdata->i2c_vdp << 1);  in adv7842_rewrite_i2c_addresses()
3394 	io_write(sd, io_reg, addr << 1);  in adv7842_dummy_client()