Lines Matching refs:stv0367_writereg
157 static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data) in stv0367_writereg() function
222 stv0367_writereg(state, (label >> 16) & 0xffff, reg); in stv0367_writebits()
269 stv0367_writereg(state, deftab[i].addr, deftab[i].value); in stv0367_write_table()
288 stv0367_writereg(state, R367TER_PLLMDIV, 0x1b); in stv0367_pll_setup()
289 stv0367_writereg(state, R367TER_PLLNDIV, 0xe8); in stv0367_pll_setup()
298 stv0367_writereg(state, R367TER_PLLMDIV, 0x2); in stv0367_pll_setup()
299 stv0367_writereg(state, R367TER_PLLNDIV, 0x1b); in stv0367_pll_setup()
302 stv0367_writereg(state, R367TER_PLLMDIV, 0xa); in stv0367_pll_setup()
303 stv0367_writereg(state, R367TER_PLLNDIV, 0x55); in stv0367_pll_setup()
308 stv0367_writereg(state, R367TER_PLLMDIV, 0x1); in stv0367_pll_setup()
309 stv0367_writereg(state, R367TER_PLLNDIV, 0x8); in stv0367_pll_setup()
312 stv0367_writereg(state, R367TER_PLLMDIV, 0xc); in stv0367_pll_setup()
313 stv0367_writereg(state, R367TER_PLLNDIV, 0x55); in stv0367_pll_setup()
318 stv0367_writereg(state, R367TER_PLLSETUP, 0x18); in stv0367_pll_setup()
347 stv0367_writereg(state, R367TER_I2CRPT, tmp); in stv0367ter_gate_ctrl()
506 stv0367_writereg(state, in stv0367ter_filt_coeff_init()
509 stv0367_writereg(state, in stv0367ter_filt_coeff_init()
775 stv0367_writereg(state, R367TER_CHC_CTL, 0x01); in stv0367ter_lock_algo()
780 stv0367_writereg(state, R367TER_CHC_CTL, 0x11); in stv0367ter_lock_algo()
824 stv0367_writereg(state, R367TER_CHC_CTL, 0x11); in stv0367ter_lock_algo()
847 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0); in stv0367ter_lock_algo()
848 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60); in stv0367ter_lock_algo()
849 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0); in stv0367ter_lock_algo()
851 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0); in stv0367ter_lock_algo()
981 stv0367_writereg(state, R367TER_I2CRPT, 0xa0); in stv0367ter_init()
982 stv0367_writereg(state, R367TER_ANACTRL, 0x00); in stv0367ter_init()
1813 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); in stv0367cab_SetQamSize()
1816 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64); in stv0367cab_SetQamSize()
1817 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); in stv0367cab_SetQamSize()
1818 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90); in stv0367cab_SetQamSize()
1819 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); in stv0367cab_SetQamSize()
1820 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); in stv0367cab_SetQamSize()
1821 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95); in stv0367cab_SetQamSize()
1822 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40); in stv0367cab_SetQamSize()
1823 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a); in stv0367cab_SetQamSize()
1826 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); in stv0367cab_SetQamSize()
1827 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e); in stv0367cab_SetQamSize()
1828 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0); in stv0367cab_SetQamSize()
1829 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); in stv0367cab_SetQamSize()
1830 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7); in stv0367cab_SetQamSize()
1831 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d); in stv0367cab_SetQamSize()
1832 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f); in stv0367cab_SetQamSize()
1833 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7); in stv0367cab_SetQamSize()
1836 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82); in stv0367cab_SetQamSize()
1837 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a); in stv0367cab_SetQamSize()
1839 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0); in stv0367cab_SetQamSize()
1840 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); in stv0367cab_SetQamSize()
1841 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5); in stv0367cab_SetQamSize()
1843 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0); in stv0367cab_SetQamSize()
1844 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); in stv0367cab_SetQamSize()
1845 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6); in stv0367cab_SetQamSize()
1847 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0); in stv0367cab_SetQamSize()
1848 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1); in stv0367cab_SetQamSize()
1849 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); in stv0367cab_SetQamSize()
1851 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95); in stv0367cab_SetQamSize()
1852 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40); in stv0367cab_SetQamSize()
1853 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99); in stv0367cab_SetQamSize()
1856 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); in stv0367cab_SetQamSize()
1857 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76); in stv0367cab_SetQamSize()
1858 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90); in stv0367cab_SetQamSize()
1859 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1); in stv0367cab_SetQamSize()
1861 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); in stv0367cab_SetQamSize()
1863 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6); in stv0367cab_SetQamSize()
1865 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97); in stv0367cab_SetQamSize()
1867 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e); in stv0367cab_SetQamSize()
1868 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f); in stv0367cab_SetQamSize()
1869 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7); in stv0367cab_SetQamSize()
1872 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94); in stv0367cab_SetQamSize()
1873 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a); in stv0367cab_SetQamSize()
1874 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0); in stv0367cab_SetQamSize()
1876 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); in stv0367cab_SetQamSize()
1878 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); in stv0367cab_SetQamSize()
1880 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1); in stv0367cab_SetQamSize()
1882 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); in stv0367cab_SetQamSize()
1883 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85); in stv0367cab_SetQamSize()
1884 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40); in stv0367cab_SetQamSize()
1885 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7); in stv0367cab_SetQamSize()
1888 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); in stv0367cab_SetQamSize()
1891 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); in stv0367cab_SetQamSize()
1926 stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if); in stv0367cab_set_derot_freq()
1927 stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8)); in stv0367cab_set_derot_freq()
1994 stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp); in stv0367cab_set_srate()
2081 stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp); in stv0367cab_set_srate()
2082 stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8)); in stv0367cab_set_srate()
2083 stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16)); in stv0367cab_set_srate()
2084 stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24)); in stv0367cab_set_srate()
2086 stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff); in stv0367cab_set_srate()
2313 stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */ in stv0367cab_init()
2402 stv0367_writereg(state, R367CAB_CTRL_1, 0x04); in stv0367cab_algo()
2429 stv0367_writereg(state, R367CAB_CTRL_1, 0x00); in stv0367cab_algo()
2930 stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00); in stv0367ddb_setup_ter()
2931 stv0367_writereg(state, R367TER_DEBUG_LT5, 0x00); in stv0367ddb_setup_ter()
2932 stv0367_writereg(state, R367TER_DEBUG_LT6, 0x00); /* R367CAB_CTRL_1 */ in stv0367ddb_setup_ter()
2933 stv0367_writereg(state, R367TER_DEBUG_LT7, 0x00); /* R367CAB_CTRL_2 */ in stv0367ddb_setup_ter()
2934 stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00); in stv0367ddb_setup_ter()
2935 stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00); in stv0367ddb_setup_ter()
2939 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x89); in stv0367ddb_setup_ter()
2940 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */ in stv0367ddb_setup_ter()
2944 stv0367_writereg(state, R367TER_ANACTRL, 0x0D); in stv0367ddb_setup_ter()
2945 stv0367_writereg(state, R367TER_TOPCTRL, 0x00); /* Set OFDM */ in stv0367ddb_setup_ter()
2952 stv0367_writereg(state, R367TER_ANACTRL, 0x00); in stv0367ddb_setup_ter()
2959 stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00); in stv0367ddb_setup_cab()
2960 stv0367_writereg(state, R367TER_DEBUG_LT5, 0x01); in stv0367ddb_setup_cab()
2961 stv0367_writereg(state, R367TER_DEBUG_LT6, 0x06); /* R367CAB_CTRL_1 */ in stv0367ddb_setup_cab()
2962 stv0367_writereg(state, R367TER_DEBUG_LT7, 0x03); /* R367CAB_CTRL_2 */ in stv0367ddb_setup_cab()
2963 stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00); in stv0367ddb_setup_cab()
2964 stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00); in stv0367ddb_setup_cab()
2968 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8B); in stv0367ddb_setup_cab()
2970 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); in stv0367ddb_setup_cab()
2974 stv0367_writereg(state, R367TER_ANACTRL, 0x0D); in stv0367ddb_setup_cab()
2976 stv0367_writereg(state, R367TER_TOPCTRL, 0x10); in stv0367ddb_setup_cab()
2983 stv0367_writereg(state, R367TER_ANACTRL, 0x00); in stv0367ddb_setup_cab()
3174 stv0367_writereg(state, R367TER_TOPCTRL, 0x10); in stv0367ddb_init()
3183 stv0367_writereg(state, R367TER_TOPCTRL, 0x00); in stv0367ddb_init()
3187 stv0367_writereg(state, R367TER_GAIN_SRC1, 0x2A); in stv0367ddb_init()
3188 stv0367_writereg(state, R367TER_GAIN_SRC2, 0xD6); in stv0367ddb_init()
3189 stv0367_writereg(state, R367TER_INC_DEROT1, 0x55); in stv0367ddb_init()
3190 stv0367_writereg(state, R367TER_INC_DEROT2, 0x55); in stv0367ddb_init()
3191 stv0367_writereg(state, R367TER_TRL_CTL, 0x14); in stv0367ddb_init()
3192 stv0367_writereg(state, R367TER_TRL_NOMRATE1, 0xAE); in stv0367ddb_init()
3193 stv0367_writereg(state, R367TER_TRL_NOMRATE2, 0x56); in stv0367ddb_init()
3194 stv0367_writereg(state, R367TER_FEPATH_CFG, 0x0); in stv0367ddb_init()
3198 stv0367_writereg(state, R367TER_TSCFGH, 0x70); in stv0367ddb_init()
3199 stv0367_writereg(state, R367TER_TSCFGM, 0xC0); in stv0367ddb_init()
3200 stv0367_writereg(state, R367TER_TSCFGL, 0x20); in stv0367ddb_init()
3201 stv0367_writereg(state, R367TER_TSSPEED, 0x40); /* Fixed at 54 MHz */ in stv0367ddb_init()
3203 stv0367_writereg(state, R367TER_TSCFGH, 0x71); in stv0367ddb_init()
3204 stv0367_writereg(state, R367TER_TSCFGH, 0x70); in stv0367ddb_init()
3206 stv0367_writereg(state, R367TER_TOPCTRL, 0x10); in stv0367ddb_init()
3209 stv0367_writereg(state, R367TER_AGC12C, 0x01); /* AGC Pin setup */ in stv0367ddb_init()
3211 stv0367_writereg(state, R367TER_AGCCTRL1, 0x8A); in stv0367ddb_init()
3216 stv0367_writereg(state, R367CAB_OUTFORMAT_0, 0x85); in stv0367ddb_init()
3219 stv0367_writereg(state, R367TER_ANACTRL, 0x0D); in stv0367ddb_init()
3226 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8b); in stv0367ddb_init()
3227 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */ in stv0367ddb_init()
3230 stv0367_writereg(state, R367CAB_FSM_SNR2_HTH, 0x23); in stv0367ddb_init()
3232 stv0367_writereg(state, R367CAB_IQ_QAM, 0x01); in stv0367ddb_init()
3234 stv0367_writereg(state, R367CAB_EQU_FFE_LEAKAGE, 0x83); in stv0367ddb_init()
3236 stv0367_writereg(state, R367CAB_IQDEM_ADJ_EN, 0x05); in stv0367ddb_init()
3239 stv0367_writereg(state, R367TER_ANACTRL, 0x00); in stv0367ddb_init()
3241 stv0367_writereg(state, R367TER_I2CRPT, (0x08 | ((5 & 0x07) << 4))); in stv0367ddb_init()