Lines Matching +full:0 +full:x3b
63 } while (0)
70 { .addr = state->config->demod_address, .flags = 0, .buf = b, .len = 2 }, in s5h1420_readreg()
71 { .addr = state->config->demod_address, .flags = 0, .buf = ®, .len = 1 }, in s5h1420_readreg()
75 b[0] = (reg - 1) & 0xff; in s5h1420_readreg()
76 b[1] = state->shadow[(reg - 1) & 0xff]; in s5h1420_readreg()
91 /* dprintk("rd(%02x): %02x %02x\n", state->config->demod_address, reg, b[0]); */ in s5h1420_readreg()
93 return b[0]; in s5h1420_readreg()
99 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; in s5h1420_writereg()
105 …dprintk("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, dat… in s5h1420_writereg()
110 return 0; in s5h1420_writereg()
122 s5h1420_writereg(state, 0x3c, in s5h1420_set_voltage()
123 (s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02); in s5h1420_set_voltage()
127 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03); in s5h1420_set_voltage()
131 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd); in s5h1420_set_voltage()
136 return 0; in s5h1420_set_voltage()
147 s5h1420_writereg(state, 0x3b, in s5h1420_set_tone()
148 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x08); in s5h1420_set_tone()
152 s5h1420_writereg(state, 0x3b, in s5h1420_set_tone()
153 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01); in s5h1420_set_tone()
158 return 0; in s5h1420_set_tone()
168 int result = 0; in s5h1420_send_master_cmd()
175 val = s5h1420_readreg(state, 0x3b); in s5h1420_send_master_cmd()
176 s5h1420_writereg(state, 0x3b, 0x02); in s5h1420_send_master_cmd()
180 for(i=0; i< cmd->msg_len; i++) { in s5h1420_send_master_cmd()
181 s5h1420_writereg(state, 0x3d + i, cmd->msg[i]); in s5h1420_send_master_cmd()
185 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | in s5h1420_send_master_cmd()
186 ((cmd->msg_len-1) << 4) | 0x08); in s5h1420_send_master_cmd()
191 if (!(s5h1420_readreg(state, 0x3b) & 0x08)) in s5h1420_send_master_cmd()
200 s5h1420_writereg(state, 0x3b, val); in s5h1420_send_master_cmd()
214 int result = 0; in s5h1420_recv_slave_reply()
217 val = s5h1420_readreg(state, 0x3b); in s5h1420_recv_slave_reply()
218 …s5h1420_writereg(state, 0x3b, 0x82); /* FIXME: guess - do we need to set DIS_RDY(0x08) in receive … in s5h1420_recv_slave_reply()
224 if (!(s5h1420_readreg(state, 0x3b) & 0x80)) /* FIXME: do we test DIS_RDY(0x08) or RCV_EN(0x80)? */ in s5h1420_recv_slave_reply()
236 if (s5h1420_readreg(state, 0x49)) { in s5h1420_recv_slave_reply()
242 length = (s5h1420_readreg(state, 0x3b) & 0x70) >> 4; in s5h1420_recv_slave_reply()
250 for(i=0; i< length; i++) { in s5h1420_recv_slave_reply()
251 reply->msg[i] = s5h1420_readreg(state, 0x3d + i); in s5h1420_recv_slave_reply()
256 s5h1420_writereg(state, 0x3b, val); in s5h1420_recv_slave_reply()
266 int result = 0; in s5h1420_send_burst()
270 val = s5h1420_readreg(state, 0x3b); in s5h1420_send_burst()
271 s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01); in s5h1420_send_burst()
275 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04); in s5h1420_send_burst()
280 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08); in s5h1420_send_burst()
285 if (!(s5h1420_readreg(state, 0x3b) & 0x08)) in s5h1420_send_burst()
294 s5h1420_writereg(state, 0x3b, val); in s5h1420_send_burst()
302 enum fe_status status = 0; in s5h1420_get_status_bits()
304 val = s5h1420_readreg(state, 0x14); in s5h1420_get_status_bits()
305 if (val & 0x02) in s5h1420_get_status_bits()
307 if (val & 0x01) in s5h1420_get_status_bits()
309 val = s5h1420_readreg(state, 0x36); in s5h1420_get_status_bits()
310 if (val & 0x01) in s5h1420_get_status_bits()
312 if (val & 0x20) in s5h1420_get_status_bits()
338 if ((val & 0x07) == 0x03) { in s5h1420_read_status()
339 if (val & 0x08) in s5h1420_read_status()
340 s5h1420_writereg(state, Vit09, 0x13); in s5h1420_read_status()
342 s5h1420_writereg(state, Vit09, 0x1b); in s5h1420_read_status()
355 switch (s5h1420_readreg(state, Vit10) & 0x07) { in s5h1420_read_status()
356 case 0: tmp = (tmp * 2 * 1) / 2; break; in s5h1420_read_status()
364 if (tmp == 0) { in s5h1420_read_status()
365 printk(KERN_ERR "s5h1420: avoided division by 0\n"); in s5h1420_read_status()
373 val = 0x00; in s5h1420_read_status()
375 val = 0x01; in s5h1420_read_status()
377 val = 0x02; in s5h1420_read_status()
379 val = 0x03; in s5h1420_read_status()
381 val = 0x04; in s5h1420_read_status()
383 val = 0x05; in s5h1420_read_status()
385 val = 0x06; in s5h1420_read_status()
387 val = 0x07; in s5h1420_read_status()
390 s5h1420_writereg(state, FEC01, 0x18); in s5h1420_read_status()
391 s5h1420_writereg(state, FEC01, 0x10); in s5h1420_read_status()
399 val = s5h1420_readreg(state, QPSK01) & 0x7f; in s5h1420_read_status()
405 s5h1420_writereg(state, Loop04, 0x8a); in s5h1420_read_status()
406 s5h1420_writereg(state, Loop05, 0x6a); in s5h1420_read_status()
408 s5h1420_writereg(state, Loop04, 0x58); in s5h1420_read_status()
409 s5h1420_writereg(state, Loop05, 0x27); in s5h1420_read_status()
418 return 0; in s5h1420_read_status()
425 s5h1420_writereg(state, 0x46, 0x1d); in s5h1420_read_ber()
428 *ber = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47); in s5h1420_read_ber()
430 return 0; in s5h1420_read_ber()
437 u8 val = s5h1420_readreg(state, 0x15); in s5h1420_read_signal_strength()
441 return 0; in s5h1420_read_signal_strength()
448 s5h1420_writereg(state, 0x46, 0x1f); in s5h1420_read_ucblocks()
451 *ucblocks = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47); in s5h1420_read_ucblocks()
453 return 0; in s5h1420_read_ucblocks()
459 s5h1420_writereg (state, 0x01, 0x08); in s5h1420_reset()
460 s5h1420_writereg (state, 0x01, 0x00); in s5h1420_reset()
480 s5h1420_writereg(state, Loop01, v & 0x7f); in s5h1420_setsymbolrate()
483 s5h1420_writereg(state, Tnco03, val & 0xff); in s5h1420_setsymbolrate()
484 s5h1420_writereg(state, Loop01, v | 0x80); in s5h1420_setsymbolrate()
507 s5h1420_writereg(state, Loop01, v & 0xbf); in s5h1420_setfreqoffset()
510 s5h1420_writereg(state, Pnco03, val & 0xff); in s5h1420_setfreqoffset()
511 s5h1420_writereg(state, Loop01, v | 0x40); in s5h1420_setfreqoffset()
519 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08); in s5h1420_getfreqoffset()
520 val = s5h1420_readreg(state, 0x0e) << 16; in s5h1420_getfreqoffset()
521 val |= s5h1420_readreg(state, 0x0f) << 8; in s5h1420_getfreqoffset()
522 val |= s5h1420_readreg(state, 0x10); in s5h1420_getfreqoffset()
523 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7); in s5h1420_getfreqoffset()
525 if (val & 0x800000) in s5h1420_getfreqoffset()
526 val |= 0xff000000; in s5h1420_getfreqoffset()
538 u8 inversion = 0; in s5h1420_setfec_inversion()
544 inversion = state->config->invert ? 0x08 : 0; in s5h1420_setfec_inversion()
546 inversion = state->config->invert ? 0 : 0x08; in s5h1420_setfec_inversion()
549 vit08 = 0x3f; in s5h1420_setfec_inversion()
550 vit09 = 0; in s5h1420_setfec_inversion()
554 vit08 = 0x01; in s5h1420_setfec_inversion()
555 vit09 = 0x10; in s5h1420_setfec_inversion()
559 vit08 = 0x02; in s5h1420_setfec_inversion()
560 vit09 = 0x11; in s5h1420_setfec_inversion()
564 vit08 = 0x04; in s5h1420_setfec_inversion()
565 vit09 = 0x12; in s5h1420_setfec_inversion()
569 vit08 = 0x08; in s5h1420_setfec_inversion()
570 vit09 = 0x13; in s5h1420_setfec_inversion()
574 vit08 = 0x10; in s5h1420_setfec_inversion()
575 vit09 = 0x14; in s5h1420_setfec_inversion()
579 vit08 = 0x20; in s5h1420_setfec_inversion()
580 vit09 = 0x15; in s5h1420_setfec_inversion()
596 switch(s5h1420_readreg(state, 0x32) & 0x07) { in s5h1420_getfec()
597 case 0: in s5h1420_getfec()
622 if (s5h1420_readreg(state, 0x32) & 0x08) in s5h1420_getinversion()
642 (frequency_delta != 0) && in s5h1420_set_frontend()
648 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); in s5h1420_set_frontend()
653 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); in s5h1420_set_frontend()
656 s5h1420_setfreqoffset(state, 0); in s5h1420_set_frontend()
659 return 0; in s5h1420_set_frontend()
680 s5h1420_writereg(state, PLL02, 0x40); in s5h1420_set_frontend()
685 s5h1420_writereg(state, QPSK01, 0xae | 0x10); in s5h1420_set_frontend()
687 s5h1420_writereg(state, QPSK01, 0xac | 0x10); in s5h1420_set_frontend()
690 s5h1420_writereg(state, CON_1, 0x00); in s5h1420_set_frontend()
691 s5h1420_writereg(state, QPSK02, 0x00); in s5h1420_set_frontend()
692 s5h1420_writereg(state, Pre01, 0xb0); in s5h1420_set_frontend()
694 s5h1420_writereg(state, Loop01, 0xF0); in s5h1420_set_frontend()
695 s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */ in s5h1420_set_frontend()
696 s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */ in s5h1420_set_frontend()
698 s5h1420_writereg(state, Loop04, 0x79); in s5h1420_set_frontend()
700 s5h1420_writereg(state, Loop04, 0x58); in s5h1420_set_frontend()
701 s5h1420_writereg(state, Loop05, 0x6b); in s5h1420_set_frontend()
704 s5h1420_writereg(state, Post01, (0 << 6) | 0x10); in s5h1420_set_frontend()
706 s5h1420_writereg(state, Post01, (1 << 6) | 0x10); in s5h1420_set_frontend()
708 s5h1420_writereg(state, Post01, (3 << 6) | 0x10); in s5h1420_set_frontend()
710 s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */ in s5h1420_set_frontend()
712 s5h1420_writereg(state, Sync01, 0x33); in s5h1420_set_frontend()
714 s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */ in s5h1420_set_frontend()
715 s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */ in s5h1420_set_frontend()
717 s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */ in s5h1420_set_frontend()
718 s5h1420_writereg(state, DiS03, 0x00); in s5h1420_set_frontend()
719 s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */ in s5h1420_set_frontend()
725 fe->ops.i2c_gate_ctrl(fe, 0); in s5h1420_set_frontend()
726 s5h1420_setfreqoffset(state, 0); in s5h1420_set_frontend()
738 state->postlocked = 0; in s5h1420_set_frontend()
742 return 0; in s5h1420_set_frontend()
755 return 0; in s5h1420_get_frontend()
788 return 0; in s5h1420_get_tune_settings()
796 return s5h1420_writereg(state, 0x02, state->CON_1_val | 1); in s5h1420_i2c_gate_ctrl()
798 return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe); in s5h1420_i2c_gate_ctrl()
807 s5h1420_writereg(state, 0x02, state->CON_1_val); in s5h1420_init()
811 return 0; in s5h1420_init()
817 state->CON_1_val = 0x12; in s5h1420_sleep()
818 return s5h1420_writereg(state, 0x02, state->CON_1_val); in s5h1420_sleep()
846 memset(m, 0, sizeof(struct i2c_msg) * (1 + num)); in s5h1420_tuner_i2c_tuner_xfer()
848 m[0].addr = state->config->demod_address; in s5h1420_tuner_i2c_tuner_xfer()
849 m[0].buf = tx_open; in s5h1420_tuner_i2c_tuner_xfer()
850 m[0].len = 2; in s5h1420_tuner_i2c_tuner_xfer()
884 state->postlocked = 0; in s5h1420_attach()
886 state->tunedfreq = 0; in s5h1420_attach()
888 state->symbol_rate = 0; in s5h1420_attach()
892 if (i != 0x03) in s5h1420_attach()
895 memset(state->shadow, 0xff, sizeof(state->shadow)); in s5h1420_attach()
897 for (i = 0; i < 0x50; i++) in s5h1420_attach()
910 if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) { in s5h1420_attach()