Lines Matching +full:0 +full:x93
37 #define QAM_STATE_UNTUNED 0
57 { 0x00, 0x0071, },
58 { 0x01, 0x3213, },
59 { 0x09, 0x0025, },
60 { 0x1c, 0x001d, },
61 { 0x1f, 0x002d, },
62 { 0x20, 0x001d, },
63 { 0x22, 0x0022, },
64 { 0x23, 0x0020, },
65 { 0x29, 0x110f, },
66 { 0x2a, 0x10b4, },
67 { 0x2b, 0x10ae, },
68 { 0x2c, 0x0031, },
69 { 0x31, 0x010d, },
70 { 0x32, 0x0100, },
71 { 0x44, 0x0510, },
72 { 0x54, 0x0104, },
73 { 0x58, 0x2222, },
74 { 0x59, 0x1162, },
75 { 0x5a, 0x3211, },
76 { 0x5d, 0x0370, },
77 { 0x5e, 0x0296, },
78 { 0x61, 0x0010, },
79 { 0x63, 0x4a00, },
80 { 0x65, 0x0800, },
81 { 0x71, 0x0003, },
82 { 0x72, 0x0470, },
83 { 0x81, 0x0002, },
84 { 0x82, 0x0600, },
85 { 0x86, 0x0002, },
86 { 0x8a, 0x2c38, },
87 { 0x8b, 0x2a37, },
88 { 0x92, 0x302f, },
89 { 0x93, 0x3332, },
90 { 0x96, 0x000c, },
91 { 0x99, 0x0101, },
92 { 0x9c, 0x2e37, },
93 { 0x9d, 0x2c37, },
94 { 0x9e, 0x2c37, },
95 { 0xab, 0x0100, },
96 { 0xac, 0x1003, },
97 { 0xad, 0x103f, },
98 { 0xe2, 0x0100, },
99 { 0xe3, 0x1000, },
100 { 0x28, 0x1010, },
101 { 0xb1, 0x000e, },
148 { 0, 0, },
156 { 1, 0, },
220 { 255, 0, },
228 { 1, 0, },
297 { 255, 0, },
304 u8 buf[] = { reg, data >> 8, data & 0xff }; in s5h1409_writereg()
307 .flags = 0, .buf = buf, .len = 3 }; in s5h1409_writereg()
312 printk(KERN_ERR "%s: error (reg == 0x%02x, val == 0x%04x, ret == %i)\n", in s5h1409_writereg()
315 return (ret != 1) ? -1 : 0; in s5h1409_writereg()
322 u8 b1[] = { 0, 0 }; in s5h1409_readreg()
325 { .addr = state->config->demod_address, .flags = 0, in s5h1409_readreg()
334 return (b1[0] << 8) | b1[1]; in s5h1409_readreg()
343 s5h1409_writereg(state, 0xf5, 0); in s5h1409_softreset()
344 s5h1409_writereg(state, 0xf5, 1); in s5h1409_softreset()
345 state->is_qam_locked = 0; in s5h1409_softreset()
347 return 0; in s5h1409_softreset()
361 s5h1409_writereg(state, 0x87, 0x014b); in s5h1409_set_if_freq()
362 s5h1409_writereg(state, 0x88, 0x0cb5); in s5h1409_set_if_freq()
363 s5h1409_writereg(state, 0x89, 0x03e2); in s5h1409_set_if_freq()
368 s5h1409_writereg(state, 0x87, 0x01be); in s5h1409_set_if_freq()
369 s5h1409_writereg(state, 0x88, 0x0436); in s5h1409_set_if_freq()
370 s5h1409_writereg(state, 0x89, 0x054d); in s5h1409_set_if_freq()
375 return 0; in s5h1409_set_if_freq()
385 return s5h1409_writereg(state, 0x1b, 0x1101); /* Inverted */ in s5h1409_set_spectralinversion()
387 return s5h1409_writereg(state, 0x1b, 0x0110); /* Normal */ in s5h1409_set_spectralinversion()
395 dprintk("%s(0x%08x)\n", __func__, m); in s5h1409_enable_modulation()
402 s5h1409_writereg(state, 0xf4, 0); in s5h1409_enable_modulation()
410 s5h1409_writereg(state, 0xf4, 1); in s5h1409_enable_modulation()
411 s5h1409_writereg(state, 0x85, 0x110); in s5h1409_enable_modulation()
421 return 0; in s5h1409_enable_modulation()
431 return s5h1409_writereg(state, 0xf3, 1); in s5h1409_i2c_gate_ctrl()
433 return s5h1409_writereg(state, 0xf3, 0); in s5h1409_i2c_gate_ctrl()
443 return s5h1409_writereg(state, 0xe3, in s5h1409_set_gpio()
444 s5h1409_readreg(state, 0xe3) | 0x1100); in s5h1409_set_gpio()
446 return s5h1409_writereg(state, 0xe3, in s5h1409_set_gpio()
447 s5h1409_readreg(state, 0xe3) & 0xfeff); in s5h1409_set_gpio()
456 return s5h1409_writereg(state, 0xf2, enable); in s5h1409_sleep()
465 return s5h1409_writereg(state, 0xfa, 0); in s5h1409_register_reset()
486 reg = s5h1409_readreg(state, 0xf0); in s5h1409_set_qam_amhum_mode()
488 if ((reg >> 13) & 0x1) { in s5h1409_set_qam_amhum_mode()
489 reg &= 0xff; in s5h1409_set_qam_amhum_mode()
491 s5h1409_writereg(state, 0x96, 0x000c); in s5h1409_set_qam_amhum_mode()
492 if (reg < 0x68) { in s5h1409_set_qam_amhum_mode()
496 s5h1409_writereg(state, 0x93, 0x3130); in s5h1409_set_qam_amhum_mode()
497 s5h1409_writereg(state, 0x9e, 0x2836); in s5h1409_set_qam_amhum_mode()
504 s5h1409_writereg(state, 0x93, 0x3332); in s5h1409_set_qam_amhum_mode()
505 s5h1409_writereg(state, 0x9e, 0x2c37); in s5h1409_set_qam_amhum_mode()
513 s5h1409_writereg(state, 0x96, 0x0008); in s5h1409_set_qam_amhum_mode()
514 s5h1409_writereg(state, 0x93, 0x3332); in s5h1409_set_qam_amhum_mode()
515 s5h1409_writereg(state, 0x9e, 0x2c37); in s5h1409_set_qam_amhum_mode()
530 reg = s5h1409_readreg(state, 0xf0); in s5h1409_set_qam_amhum_mode_legacy()
532 if ((reg >> 13) & 0x1) { in s5h1409_set_qam_amhum_mode_legacy()
535 reg &= 0xff; in s5h1409_set_qam_amhum_mode_legacy()
537 s5h1409_writereg(state, 0x96, 0x00c); in s5h1409_set_qam_amhum_mode_legacy()
538 if ((reg < 0x38) || (reg > 0x68)) { in s5h1409_set_qam_amhum_mode_legacy()
539 s5h1409_writereg(state, 0x93, 0x3332); in s5h1409_set_qam_amhum_mode_legacy()
540 s5h1409_writereg(state, 0x9e, 0x2c37); in s5h1409_set_qam_amhum_mode_legacy()
542 s5h1409_writereg(state, 0x93, 0x3130); in s5h1409_set_qam_amhum_mode_legacy()
543 s5h1409_writereg(state, 0x9e, 0x2836); in s5h1409_set_qam_amhum_mode_legacy()
547 s5h1409_writereg(state, 0x96, 0x0008); in s5h1409_set_qam_amhum_mode_legacy()
548 s5h1409_writereg(state, 0x93, 0x3332); in s5h1409_set_qam_amhum_mode_legacy()
549 s5h1409_writereg(state, 0x9e, 0x2c37); in s5h1409_set_qam_amhum_mode_legacy()
563 reg = s5h1409_readreg(state, 0xf1); in s5h1409_set_qam_interleave_mode()
566 if ((reg >> 15) & 0x1) { in s5h1409_set_qam_interleave_mode()
571 reg1 = s5h1409_readreg(state, 0xb2); in s5h1409_set_qam_interleave_mode()
572 reg2 = s5h1409_readreg(state, 0xad); in s5h1409_set_qam_interleave_mode()
574 s5h1409_writereg(state, 0x96, 0x0020); in s5h1409_set_qam_interleave_mode()
575 s5h1409_writereg(state, 0xad, in s5h1409_set_qam_interleave_mode()
576 (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff))); in s5h1409_set_qam_interleave_mode()
583 s5h1409_writereg(state, 0x96, 0x08); in s5h1409_set_qam_interleave_mode()
584 s5h1409_writereg(state, 0xab, in s5h1409_set_qam_interleave_mode()
585 s5h1409_readreg(state, 0xab) | 0x1001); in s5h1409_set_qam_interleave_mode()
596 reg = s5h1409_readreg(state, 0xf1); in s5h1409_set_qam_interleave_mode_legacy()
599 if ((reg >> 15) & 0x1) { in s5h1409_set_qam_interleave_mode_legacy()
602 reg1 = s5h1409_readreg(state, 0xb2); in s5h1409_set_qam_interleave_mode_legacy()
603 reg2 = s5h1409_readreg(state, 0xad); in s5h1409_set_qam_interleave_mode_legacy()
605 s5h1409_writereg(state, 0x96, 0x20); in s5h1409_set_qam_interleave_mode_legacy()
606 s5h1409_writereg(state, 0xad, in s5h1409_set_qam_interleave_mode_legacy()
607 (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff))); in s5h1409_set_qam_interleave_mode_legacy()
608 s5h1409_writereg(state, 0xab, in s5h1409_set_qam_interleave_mode_legacy()
609 s5h1409_readreg(state, 0xab) & 0xeffe); in s5h1409_set_qam_interleave_mode_legacy()
614 s5h1409_writereg(state, 0x96, 0x08); in s5h1409_set_qam_interleave_mode_legacy()
615 s5h1409_writereg(state, 0xab, in s5h1409_set_qam_interleave_mode_legacy()
616 s5h1409_readreg(state, 0xab) | 0x1001); in s5h1409_set_qam_interleave_mode_legacy()
640 fe->ops.i2c_gate_ctrl(fe, 0); in s5h1409_set_frontend()
661 return 0; in s5h1409_set_frontend()
671 val = s5h1409_readreg(state, 0xac) & 0xcfff; in s5h1409_set_mpeg_timing()
674 val |= 0x0000; in s5h1409_set_mpeg_timing()
678 val |= 0x1000; in s5h1409_set_mpeg_timing()
681 val |= 0x2000; in s5h1409_set_mpeg_timing()
684 val |= 0x3000; in s5h1409_set_mpeg_timing()
691 return s5h1409_writereg(state, 0xac, val); in s5h1409_set_mpeg_timing()
703 s5h1409_sleep(fe, 0); in s5h1409_init()
706 for (i = 0; i < ARRAY_SIZE(init_tab); i++) in s5h1409_init()
717 s5h1409_writereg(state, 0x09, 0x0050); in s5h1409_init()
720 s5h1409_writereg(state, 0x21, 0x0001); in s5h1409_init()
721 s5h1409_writereg(state, 0x50, 0x030e); in s5h1409_init()
724 s5h1409_writereg(state, 0x82, 0x0800); in s5h1409_init()
728 s5h1409_writereg(state, 0xab, in s5h1409_init()
729 s5h1409_readreg(state, 0xab) | 0x100); /* Serial */ in s5h1409_init()
731 s5h1409_writereg(state, 0xab, in s5h1409_init()
732 s5h1409_readreg(state, 0xab) & 0xfeff); /* Parallel */ in s5h1409_init()
741 s5h1409_i2c_gate_ctrl(fe, 0); in s5h1409_init()
743 return 0; in s5h1409_init()
750 u32 tuner_status = 0; in s5h1409_read_status()
752 *status = 0; in s5h1409_read_status()
766 reg = s5h1409_readreg(state, 0xf1); in s5h1409_read_status()
767 if (reg & 0x1000) in s5h1409_read_status()
769 if (reg & 0x8000) in s5h1409_read_status()
786 fe->ops.i2c_gate_ctrl(fe, 0); in s5h1409_read_status()
793 dprintk("%s() status 0x%08x\n", __func__, *status); in s5h1409_read_status()
795 return 0; in s5h1409_read_status()
803 for (i = 0; i < ARRAY_SIZE(qam256_snr_tab); i++) { in s5h1409_qam256_lookup_snr()
806 ret = 0; in s5h1409_qam256_lookup_snr()
818 for (i = 0; i < ARRAY_SIZE(qam64_snr_tab); i++) { in s5h1409_qam64_lookup_snr()
821 ret = 0; in s5h1409_qam64_lookup_snr()
833 for (i = 0; i < ARRAY_SIZE(vsb_snr_tab); i++) { in s5h1409_vsb_lookup_snr()
836 ret = 0; in s5h1409_vsb_lookup_snr()
852 reg = s5h1409_readreg(state, 0xf0) & 0xff; in s5h1409_read_snr()
855 reg = s5h1409_readreg(state, 0xf0) & 0xff; in s5h1409_read_snr()
858 reg = s5h1409_readreg(state, 0xf1) & 0x3ff; in s5h1409_read_snr()
881 *signal_strength = 0; in s5h1409_read_signal_strength()
883 if (0 == ret) { in s5h1409_read_signal_strength()
892 * scale the range 0 - 35*2^24 into 0 - 65535*/ in s5h1409_read_signal_strength()
893 if (tmp >= 8960 * 0x10000) in s5h1409_read_signal_strength()
894 *signal_strength = 0xffff; in s5h1409_read_signal_strength()
906 *ucblocks = s5h1409_readreg(state, 0xb5); in s5h1409_read_ucblocks()
908 return 0; in s5h1409_read_ucblocks()
924 return 0; in s5h1409_get_frontend()
931 return 0; in s5h1409_get_tune_settings()
956 state->current_modulation = 0; in s5h1409_attach()
960 reg = s5h1409_readreg(state, 0x04); in s5h1409_attach()
961 if ((reg != 0x0066) && (reg != 0x007f)) in s5h1409_attach()
969 if (s5h1409_init(&state->frontend) != 0) { in s5h1409_attach()