228 	int status;  in i2c_write()  local
234 	status = drxk_i2c_transfer(state, &msg, 1);  in i2c_write()
235 	if (status >= 0 && status != 1)  in i2c_write()
236 		status = -EIO;  in i2c_write()
238 	if (status < 0)  in i2c_write()
241 	return status;  in i2c_write()
247 	int status;  in i2c_read()  local
255 	status = drxk_i2c_transfer(state, msgs, 2);  in i2c_read()
256 	if (status != 2) {  in i2c_read()
259 		if (status >= 0)  in i2c_read()
260 			status = -EIO;  in i2c_read()
263 		return status;  in i2c_read()
271 	int status;  in read16_flags()  local
289 	status = i2c_read(state, adr, mm1, len, mm2, 2);  in read16_flags()
290 	if (status < 0)  in read16_flags()
291 		return status;  in read16_flags()
305 	int status;  in read32_flags()  local
323 	status = i2c_read(state, adr, mm1, len, mm2, 4);  in read32_flags()
324 	if (status < 0)  in read32_flags()
325 		return status;  in read32_flags()
401 	int status = 0, blk_size = block_size;  in write_block()  local
432 		status = i2c_write(state, state->demod_address,  in write_block()
434 		if (status < 0) {  in write_block()
443 	return status;  in write_block()
452 	int status;  in power_up_device()  local
458 	status = i2c_read1(state, state->demod_address, &data);  in power_up_device()
459 	if (status < 0) {  in power_up_device()
462 			status = i2c_write(state, state->demod_address,  in power_up_device()
466 			if (status < 0)  in power_up_device()
468 			status = i2c_read1(state, state->demod_address,  in power_up_device()
470 		} while (status < 0 &&  in power_up_device()
472 		if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)  in power_up_device()
477 	status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);  in power_up_device()
478 	if (status < 0)  in power_up_device()
480 	status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in power_up_device()
481 	if (status < 0)  in power_up_device()
484 	status = write16(state, SIO_CC_PLL_LOCK__A, 1);  in power_up_device()
485 	if (status < 0)  in power_up_device()
491 	if (status < 0)  in power_up_device()
492 		pr_err("Error %d on %s\n", status, __func__);  in power_up_device()
494 	return status;  in power_up_device()
735 	int status = 0;  in drxx_open()  local
742 	status = write16(state, SCU_RAM_GPIO__A,  in drxx_open()
744 	if (status < 0)  in drxx_open()
747 	status = read16(state, SIO_TOP_COMM_KEY__A, &key);  in drxx_open()
748 	if (status < 0)  in drxx_open()
750 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in drxx_open()
751 	if (status < 0)  in drxx_open()
753 	status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);  in drxx_open()
754 	if (status < 0)  in drxx_open()
756 	status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);  in drxx_open()
757 	if (status < 0)  in drxx_open()
759 	status = write16(state, SIO_TOP_COMM_KEY__A, key);  in drxx_open()
761 	if (status < 0)  in drxx_open()
762 		pr_err("Error %d on %s\n", status, __func__);  in drxx_open()
763 	return status;  in drxx_open()
770 	int status;  in get_device_capabilities()  local
777 	status = write16(state, SCU_RAM_GPIO__A,  in get_device_capabilities()
779 	if (status < 0)  in get_device_capabilities()
781 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in get_device_capabilities()
782 	if (status < 0)  in get_device_capabilities()
784 	status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);  in get_device_capabilities()
785 	if (status < 0)  in get_device_capabilities()
787 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);  in get_device_capabilities()
788 	if (status < 0)  in get_device_capabilities()
815 	status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);  in get_device_capabilities()
816 	if (status < 0)  in get_device_capabilities()
837 		status = -EINVAL;  in get_device_capabilities()
949 		status = -EINVAL;  in get_device_capabilities()
959 	if (status < 0)  in get_device_capabilities()
960 		pr_err("Error %d on %s\n", status, __func__);  in get_device_capabilities()
963 	return status;  in get_device_capabilities()
968 	int status;  in hi_command()  local
974 	status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);  in hi_command()
975 	if (status < 0)  in hi_command()
993 			status = read16(state, SIO_HI_RA_RAM_CMD__A,  in hi_command()
995 		} while ((status < 0 || wait_cmd) && (retry_count < DRXK_MAX_RETRIES));  in hi_command()
996 		if (status < 0)  in hi_command()
998 		status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);  in hi_command()
1001 	if (status < 0)  in hi_command()
1002 		pr_err("Error %d on %s\n", status, __func__);  in hi_command()
1004 	return status;  in hi_command()
1009 	int status;  in hi_cfg_command()  local
1015 	status = write16(state, SIO_HI_RA_RAM_PAR_6__A,  in hi_cfg_command()
1017 	if (status < 0)  in hi_cfg_command()
1019 	status = write16(state, SIO_HI_RA_RAM_PAR_5__A,  in hi_cfg_command()
1021 	if (status < 0)  in hi_cfg_command()
1023 	status = write16(state, SIO_HI_RA_RAM_PAR_4__A,  in hi_cfg_command()
1025 	if (status < 0)  in hi_cfg_command()
1027 	status = write16(state, SIO_HI_RA_RAM_PAR_3__A,  in hi_cfg_command()
1029 	if (status < 0)  in hi_cfg_command()
1031 	status = write16(state, SIO_HI_RA_RAM_PAR_2__A,  in hi_cfg_command()
1033 	if (status < 0)  in hi_cfg_command()
1035 	status = write16(state, SIO_HI_RA_RAM_PAR_1__A,  in hi_cfg_command()
1037 	if (status < 0)  in hi_cfg_command()
1039 	status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);  in hi_cfg_command()
1040 	if (status < 0)  in hi_cfg_command()
1046 	if (status < 0)  in hi_cfg_command()
1047 		pr_err("Error %d on %s\n", status, __func__);  in hi_cfg_command()
1048 	return status;  in hi_cfg_command()
1065 	int status;  in mpegts_configure_pins()  local
1075 	status = write16(state, SCU_RAM_GPIO__A,  in mpegts_configure_pins()
1077 	if (status < 0)  in mpegts_configure_pins()
1081 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in mpegts_configure_pins()
1082 	if (status < 0)  in mpegts_configure_pins()
1087 		status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);  in mpegts_configure_pins()
1088 		if (status < 0)  in mpegts_configure_pins()
1090 		status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);  in mpegts_configure_pins()
1091 		if (status < 0)  in mpegts_configure_pins()
1093 		status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);  in mpegts_configure_pins()
1094 		if (status < 0)  in mpegts_configure_pins()
1096 		status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);  in mpegts_configure_pins()
1097 		if (status < 0)  in mpegts_configure_pins()
1099 		status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);  in mpegts_configure_pins()
1100 		if (status < 0)  in mpegts_configure_pins()
1102 		status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);  in mpegts_configure_pins()
1103 		if (status < 0)  in mpegts_configure_pins()
1105 		status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);  in mpegts_configure_pins()
1106 		if (status < 0)  in mpegts_configure_pins()
1108 		status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);  in mpegts_configure_pins()
1109 		if (status < 0)  in mpegts_configure_pins()
1111 		status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);  in mpegts_configure_pins()
1112 		if (status < 0)  in mpegts_configure_pins()
1114 		status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);  in mpegts_configure_pins()
1115 		if (status < 0)  in mpegts_configure_pins()
1117 		status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);  in mpegts_configure_pins()
1118 		if (status < 0)  in mpegts_configure_pins()
1120 		status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);  in mpegts_configure_pins()
1121 		if (status < 0)  in mpegts_configure_pins()
1132 		status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);  in mpegts_configure_pins()
1133 		if (status < 0)  in mpegts_configure_pins()
1139 		status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);  in mpegts_configure_pins()
1140 		if (status < 0)  in mpegts_configure_pins()
1142 		status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);  in mpegts_configure_pins()
1143 		if (status < 0)  in mpegts_configure_pins()
1148 			status = write16(state, SIO_PDR_MD1_CFG__A,  in mpegts_configure_pins()
1150 			if (status < 0)  in mpegts_configure_pins()
1152 			status = write16(state, SIO_PDR_MD2_CFG__A,  in mpegts_configure_pins()
1154 			if (status < 0)  in mpegts_configure_pins()
1156 			status = write16(state, SIO_PDR_MD3_CFG__A,  in mpegts_configure_pins()
1158 			if (status < 0)  in mpegts_configure_pins()
1160 			status = write16(state, SIO_PDR_MD4_CFG__A,  in mpegts_configure_pins()
1162 			if (status < 0)  in mpegts_configure_pins()
1164 			status = write16(state, SIO_PDR_MD5_CFG__A,  in mpegts_configure_pins()
1166 			if (status < 0)  in mpegts_configure_pins()
1168 			status = write16(state, SIO_PDR_MD6_CFG__A,  in mpegts_configure_pins()
1170 			if (status < 0)  in mpegts_configure_pins()
1172 			status = write16(state, SIO_PDR_MD7_CFG__A,  in mpegts_configure_pins()
1174 			if (status < 0)  in mpegts_configure_pins()
1181 			status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);  in mpegts_configure_pins()
1182 			if (status < 0)  in mpegts_configure_pins()
1184 			status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);  in mpegts_configure_pins()
1185 			if (status < 0)  in mpegts_configure_pins()
1187 			status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);  in mpegts_configure_pins()
1188 			if (status < 0)  in mpegts_configure_pins()
1190 			status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);  in mpegts_configure_pins()
1191 			if (status < 0)  in mpegts_configure_pins()
1193 			status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);  in mpegts_configure_pins()
1194 			if (status < 0)  in mpegts_configure_pins()
1196 			status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);  in mpegts_configure_pins()
1197 			if (status < 0)  in mpegts_configure_pins()
1199 			status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);  in mpegts_configure_pins()
1200 			if (status < 0)  in mpegts_configure_pins()
1203 		status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);  in mpegts_configure_pins()
1204 		if (status < 0)  in mpegts_configure_pins()
1206 		status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);  in mpegts_configure_pins()
1207 		if (status < 0)  in mpegts_configure_pins()
1211 	status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);  in mpegts_configure_pins()
1212 	if (status < 0)  in mpegts_configure_pins()
1215 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);  in mpegts_configure_pins()
1217 	if (status < 0)  in mpegts_configure_pins()
1218 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_configure_pins()
1219 	return status;  in mpegts_configure_pins()
1233 	int status;  in bl_chain_cmd()  local
1238 	status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);  in bl_chain_cmd()
1239 	if (status < 0)  in bl_chain_cmd()
1241 	status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);  in bl_chain_cmd()
1242 	if (status < 0)  in bl_chain_cmd()
1244 	status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);  in bl_chain_cmd()
1245 	if (status < 0)  in bl_chain_cmd()
1247 	status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);  in bl_chain_cmd()
1248 	if (status < 0)  in bl_chain_cmd()
1254 		status = read16(state, SIO_BL_STATUS__A, &bl_status);  in bl_chain_cmd()
1255 		if (status < 0)  in bl_chain_cmd()
1262 		status = -EINVAL;  in bl_chain_cmd()
1266 	if (status < 0)  in bl_chain_cmd()
1267 		pr_err("Error %d on %s\n", status, __func__);  in bl_chain_cmd()
1270 	return status;  in bl_chain_cmd()
1283 	int status = 0;  in download_microcode()  local
1327 		status = write_block(state, address, block_size, p_src);  in download_microcode()
1328 		if (status < 0) {  in download_microcode()
1329 			pr_err("Error %d while loading firmware\n", status);  in download_microcode()
1335 	return status;  in download_microcode()
1340 	int status;  in dvbt_enable_ofdm_token_ring()  local
1353 	status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);  in dvbt_enable_ofdm_token_ring()
1354 	if (status >= 0 && data == desired_status) {  in dvbt_enable_ofdm_token_ring()
1356 		return status;  in dvbt_enable_ofdm_token_ring()
1359 	status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);  in dvbt_enable_ofdm_token_ring()
1363 		status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);  in dvbt_enable_ofdm_token_ring()
1364 		if ((status >= 0 && data == desired_status)  in dvbt_enable_ofdm_token_ring()
1373 	return status;  in dvbt_enable_ofdm_token_ring()
1378 	int status = 0;  in mpegts_stop()  local
1385 	status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);  in mpegts_stop()
1386 	if (status < 0)  in mpegts_stop()
1389 	status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);  in mpegts_stop()
1390 	if (status < 0)  in mpegts_stop()
1394 	status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);  in mpegts_stop()
1395 	if (status < 0)  in mpegts_stop()
1398 	status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);  in mpegts_stop()
1401 	if (status < 0)  in mpegts_stop()
1402 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_stop()
1404 	return status;  in mpegts_stop()
1415 	int status = -EINVAL;  in scu_command()  local
1426 		pr_err("Error %d on %s\n", status, __func__);  in scu_command()
1427 		return status;  in scu_command()
1449 		status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);  in scu_command()
1450 		if (status < 0)  in scu_command()
1455 		status = -EIO;  in scu_command()
1464 			status = read16(state, SCU_RAM_PARAM_0__A - ii,  in scu_command()
1466 			if (status < 0)  in scu_command()
1495 		status = -EINVAL;  in scu_command()
1500 	if (status < 0)  in scu_command()
1501 		pr_err("Error %d on %s\n", status, __func__);  in scu_command()
1504 	return status;  in scu_command()
1510 	int status;  in set_iqm_af()  local
1515 	status = read16(state, IQM_AF_STDBY__A, &data);  in set_iqm_af()
1516 	if (status < 0)  in set_iqm_af()
1533 	status = write16(state, IQM_AF_STDBY__A, data);  in set_iqm_af()
1536 	if (status < 0)  in set_iqm_af()
1537 		pr_err("Error %d on %s\n", status, __func__);  in set_iqm_af()
1538 	return status;  in set_iqm_af()
1543 	int status = 0;  in ctrl_power_mode()  local
1579 		status = power_up_device(state);  in ctrl_power_mode()
1580 		if (status < 0)  in ctrl_power_mode()
1582 		status = dvbt_enable_ofdm_token_ring(state, true);  in ctrl_power_mode()
1583 		if (status < 0)  in ctrl_power_mode()
1601 			status = mpegts_stop(state);  in ctrl_power_mode()
1602 			if (status < 0)  in ctrl_power_mode()
1604 			status = power_down_dvbt(state, false);  in ctrl_power_mode()
1605 			if (status < 0)  in ctrl_power_mode()
1610 			status = mpegts_stop(state);  in ctrl_power_mode()
1611 			if (status < 0)  in ctrl_power_mode()
1613 			status = power_down_qam(state);  in ctrl_power_mode()
1614 			if (status < 0)  in ctrl_power_mode()
1620 		status = dvbt_enable_ofdm_token_ring(state, false);  in ctrl_power_mode()
1621 		if (status < 0)  in ctrl_power_mode()
1623 		status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);  in ctrl_power_mode()
1624 		if (status < 0)  in ctrl_power_mode()
1626 		status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in ctrl_power_mode()
1627 		if (status < 0)  in ctrl_power_mode()
1633 			status = hi_cfg_command(state);  in ctrl_power_mode()
1634 			if (status < 0)  in ctrl_power_mode()
1641 	if (status < 0)  in ctrl_power_mode()
1642 		pr_err("Error %d on %s\n", status, __func__);  in ctrl_power_mode()
1644 	return status;  in ctrl_power_mode()
1652 	int status;  in power_down_dvbt()  local
1656 	status = read16(state, SCU_COMM_EXEC__A, &data);  in power_down_dvbt()
1657 	if (status < 0)  in power_down_dvbt()
1661 		status = scu_command(state,  in power_down_dvbt()
1665 		if (status < 0)  in power_down_dvbt()
1668 		status = scu_command(state,  in power_down_dvbt()
1672 		if (status < 0)  in power_down_dvbt()
1677 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);  in power_down_dvbt()
1678 	if (status < 0)  in power_down_dvbt()
1680 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);  in power_down_dvbt()
1681 	if (status < 0)  in power_down_dvbt()
1683 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);  in power_down_dvbt()
1684 	if (status < 0)  in power_down_dvbt()
1688 	status = set_iqm_af(state, false);  in power_down_dvbt()
1689 	if (status < 0)  in power_down_dvbt()
1694 		status = ctrl_power_mode(state, &power_mode);  in power_down_dvbt()
1695 		if (status < 0)  in power_down_dvbt()
1699 	if (status < 0)  in power_down_dvbt()
1700 		pr_err("Error %d on %s\n", status, __func__);  in power_down_dvbt()
1701 	return status;  in power_down_dvbt()
1707 	int status = 0;  in setoperation_mode()  local
1717 	status = write16(state, SCU_RAM_GPIO__A,  in setoperation_mode()
1719 	if (status < 0)  in setoperation_mode()
1731 		status = mpegts_stop(state);  in setoperation_mode()
1732 		if (status < 0)  in setoperation_mode()
1734 		status = power_down_dvbt(state, true);  in setoperation_mode()
1735 		if (status < 0)  in setoperation_mode()
1741 		status = mpegts_stop(state);  in setoperation_mode()
1742 		if (status < 0)  in setoperation_mode()
1744 		status = power_down_qam(state);  in setoperation_mode()
1745 		if (status < 0)  in setoperation_mode()
1751 		status = -EINVAL;  in setoperation_mode()
1762 		status = set_dvbt_standard(state, o_mode);  in setoperation_mode()
1763 		if (status < 0)  in setoperation_mode()
1771 		status = set_qam_standard(state, o_mode);  in setoperation_mode()
1772 		if (status < 0)  in setoperation_mode()
1777 		status = -EINVAL;  in setoperation_mode()
1780 	if (status < 0)  in setoperation_mode()
1781 		pr_err("Error %d on %s\n", status, __func__);  in setoperation_mode()
1782 	return status;  in setoperation_mode()
1788 	int status = -EINVAL;  in start()  local
1809 		status = set_qam(state, i_freqk_hz, offsetk_hz);  in start()
1810 		if (status < 0)  in start()
1816 		status = mpegts_stop(state);  in start()
1817 		if (status < 0)  in start()
1819 		status = set_dvbt(state, i_freqk_hz, offsetk_hz);  in start()
1820 		if (status < 0)  in start()
1822 		status = dvbt_start(state);  in start()
1823 		if (status < 0)  in start()
1831 	if (status < 0)  in start()
1832 		pr_err("Error %d on %s\n", status, __func__);  in start()
1833 	return status;  in start()
1846 	int status = -EINVAL;  in get_lock_status()  local
1860 		status = get_qam_lock_status(state, p_lock_status);  in get_lock_status()
1863 		status = get_dvbt_lock_status(state, p_lock_status);  in get_lock_status()
1871 	if (status < 0)  in get_lock_status()
1872 		pr_err("Error %d on %s\n", status, __func__);  in get_lock_status()
1873 	return status;  in get_lock_status()
1878 	int status;  in mpegts_start()  local
1883 	status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);  in mpegts_start()
1884 	if (status < 0)  in mpegts_start()
1887 	status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);  in mpegts_start()
1888 	if (status < 0)  in mpegts_start()
1890 	status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);  in mpegts_start()
1892 	if (status < 0)  in mpegts_start()
1893 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_start()
1894 	return status;  in mpegts_start()
1899 	int status;  in mpegts_dto_init()  local
1904 	status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);  in mpegts_dto_init()
1905 	if (status < 0)  in mpegts_dto_init()
1907 	status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);  in mpegts_dto_init()
1908 	if (status < 0)  in mpegts_dto_init()
1910 	status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);  in mpegts_dto_init()
1911 	if (status < 0)  in mpegts_dto_init()
1913 	status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);  in mpegts_dto_init()
1914 	if (status < 0)  in mpegts_dto_init()
1916 	status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);  in mpegts_dto_init()
1917 	if (status < 0)  in mpegts_dto_init()
1919 	status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);  in mpegts_dto_init()
1920 	if (status < 0)  in mpegts_dto_init()
1922 	status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);  in mpegts_dto_init()
1923 	if (status < 0)  in mpegts_dto_init()
1925 	status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);  in mpegts_dto_init()
1926 	if (status < 0)  in mpegts_dto_init()
1930 	status = write16(state, FEC_OC_OCR_INVERT__A, 0);  in mpegts_dto_init()
1931 	if (status < 0)  in mpegts_dto_init()
1933 	status = write16(state, FEC_OC_SNC_LWM__A, 2);  in mpegts_dto_init()
1934 	if (status < 0)  in mpegts_dto_init()
1936 	status = write16(state, FEC_OC_SNC_HWM__A, 12);  in mpegts_dto_init()
1938 	if (status < 0)  in mpegts_dto_init()
1939 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_dto_init()
1941 	return status;  in mpegts_dto_init()
1947 	int status;  in mpegts_dto_setup()  local
1964 	status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);  in mpegts_dto_setup()
1965 	if (status < 0)  in mpegts_dto_setup()
1967 	status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);  in mpegts_dto_setup()
1968 	if (status < 0)  in mpegts_dto_setup()
2003 		status = -EINVAL;  in mpegts_dto_setup()
2005 	if (status < 0)  in mpegts_dto_setup()
2047 	status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);  in mpegts_dto_setup()
2048 	if (status < 0)  in mpegts_dto_setup()
2050 	status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);  in mpegts_dto_setup()
2051 	if (status < 0)  in mpegts_dto_setup()
2053 	status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);  in mpegts_dto_setup()
2054 	if (status < 0)  in mpegts_dto_setup()
2056 	status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);  in mpegts_dto_setup()
2057 	if (status < 0)  in mpegts_dto_setup()
2059 	status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);  in mpegts_dto_setup()
2060 	if (status < 0)  in mpegts_dto_setup()
2062 	status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);  in mpegts_dto_setup()
2063 	if (status < 0)  in mpegts_dto_setup()
2067 	status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);  in mpegts_dto_setup()
2068 	if (status < 0)  in mpegts_dto_setup()
2070 	status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,  in mpegts_dto_setup()
2072 	if (status < 0)  in mpegts_dto_setup()
2074 	status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);  in mpegts_dto_setup()
2076 	if (status < 0)  in mpegts_dto_setup()
2077 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_dto_setup()
2078 	return status;  in mpegts_dto_setup()
2119 	int status = -EINVAL;  in set_agc_rf()  local
2131 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_rf()
2132 		if (status < 0)  in set_agc_rf()
2135 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_rf()
2136 		if (status < 0)  in set_agc_rf()
2138 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_rf()
2139 		if (status < 0)  in set_agc_rf()
2150 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_rf()
2151 		if (status < 0)  in set_agc_rf()
2155 		status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);  in set_agc_rf()
2156 		if (status < 0)  in set_agc_rf()
2164 		status = write16(state, SCU_RAM_AGC_KI_RED__A, data);  in set_agc_rf()
2165 		if (status < 0)  in set_agc_rf()
2175 			status = -EINVAL;  in set_agc_rf()
2181 			status = write16(state,  in set_agc_rf()
2184 			if (status < 0)  in set_agc_rf()
2189 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,  in set_agc_rf()
2191 		if (status < 0)  in set_agc_rf()
2195 		status = write16(state, SCU_RAM_AGC_RF_MAX__A,  in set_agc_rf()
2197 		if (status < 0)  in set_agc_rf()
2204 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_rf()
2205 		if (status < 0)  in set_agc_rf()
2208 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_rf()
2209 		if (status < 0)  in set_agc_rf()
2213 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_rf()
2214 		if (status < 0)  in set_agc_rf()
2221 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_rf()
2222 		if (status < 0)  in set_agc_rf()
2226 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);  in set_agc_rf()
2227 		if (status < 0)  in set_agc_rf()
2231 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,  in set_agc_rf()
2233 		if (status < 0)  in set_agc_rf()
2239 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_rf()
2240 		if (status < 0)  in set_agc_rf()
2243 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_rf()
2244 		if (status < 0)  in set_agc_rf()
2248 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_rf()
2249 		if (status < 0)  in set_agc_rf()
2252 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_rf()
2253 		if (status < 0)  in set_agc_rf()
2258 		status = -EINVAL;  in set_agc_rf()
2262 	if (status < 0)  in set_agc_rf()
2263 		pr_err("Error %d on %s\n", status, __func__);  in set_agc_rf()
2264 	return status;  in set_agc_rf()
2273 	int status = 0;  in set_agc_if()  local
2282 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_if()
2283 		if (status < 0)  in set_agc_if()
2286 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_if()
2287 		if (status < 0)  in set_agc_if()
2290 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_if()
2291 		if (status < 0)  in set_agc_if()
2302 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_if()
2303 		if (status < 0)  in set_agc_if()
2307 		status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);  in set_agc_if()
2308 		if (status < 0)  in set_agc_if()
2315 		status = write16(state, SCU_RAM_AGC_KI_RED__A, data);  in set_agc_if()
2316 		if (status < 0)  in set_agc_if()
2326 		status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,  in set_agc_if()
2328 		if (status < 0)  in set_agc_if()
2335 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_if()
2336 		if (status < 0)  in set_agc_if()
2339 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_if()
2340 		if (status < 0)  in set_agc_if()
2343 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_if()
2344 		if (status < 0)  in set_agc_if()
2355 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_if()
2356 		if (status < 0)  in set_agc_if()
2360 		status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,  in set_agc_if()
2362 		if (status < 0)  in set_agc_if()
2369 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_if()
2370 		if (status < 0)  in set_agc_if()
2373 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_if()
2374 		if (status < 0)  in set_agc_if()
2378 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_if()
2379 		if (status < 0)  in set_agc_if()
2382 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_if()
2383 		if (status < 0)  in set_agc_if()
2390 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);  in set_agc_if()
2392 	if (status < 0)  in set_agc_if()
2393 		pr_err("Error %d on %s\n", status, __func__);  in set_agc_if()
2394 	return status;  in set_agc_if()
2400 	int status = 0;  in get_qam_signal_to_noise()  local
2412 	status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);  in get_qam_signal_to_noise()
2413 	if (status < 0) {  in get_qam_signal_to_noise()
2414 		pr_err("Error %d on %s\n", status, __func__);  in get_qam_signal_to_noise()
2443 	return status;  in get_qam_signal_to_noise()
2449 	int status;  in get_dvbt_signal_to_noise()  local
2466 	status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,  in get_dvbt_signal_to_noise()
2468 	if (status < 0)  in get_dvbt_signal_to_noise()
2470 	status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,  in get_dvbt_signal_to_noise()
2472 	if (status < 0)  in get_dvbt_signal_to_noise()
2474 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,  in get_dvbt_signal_to_noise()
2476 	if (status < 0)  in get_dvbt_signal_to_noise()
2478 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,  in get_dvbt_signal_to_noise()
2480 	if (status < 0)  in get_dvbt_signal_to_noise()
2488 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &reg_data);  in get_dvbt_signal_to_noise()
2489 	if (status < 0)  in get_dvbt_signal_to_noise()
2497 	status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,  in get_dvbt_signal_to_noise()
2499 	if (status < 0)  in get_dvbt_signal_to_noise()
2545 	if (status < 0)  in get_dvbt_signal_to_noise()
2546 		pr_err("Error %d on %s\n", status, __func__);  in get_dvbt_signal_to_noise()
2547 	return status;  in get_dvbt_signal_to_noise()
2571 	int status = 0;
2602 		status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2603 		if (status < 0)
2605 		status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2607 		if (status < 0)
2611 		status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2613 		if (status < 0)
2637 	int status = 0;
2647 		status = get_qam_signal_to_noise(state, &signal_to_noise);
2648 		if (status < 0)
2679 	return status;
2714 	int status = -EINVAL;  in ConfigureI2CBridge()  local
2726 	status = write16(state, SIO_HI_RA_RAM_PAR_1__A,  in ConfigureI2CBridge()
2728 	if (status < 0)  in ConfigureI2CBridge()
2731 		status = write16(state, SIO_HI_RA_RAM_PAR_2__A,  in ConfigureI2CBridge()
2733 		if (status < 0)  in ConfigureI2CBridge()
2736 		status = write16(state, SIO_HI_RA_RAM_PAR_2__A,  in ConfigureI2CBridge()
2738 		if (status < 0)  in ConfigureI2CBridge()
2742 	status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);  in ConfigureI2CBridge()
2745 	if (status < 0)  in ConfigureI2CBridge()
2746 		pr_err("Error %d on %s\n", status, __func__);  in ConfigureI2CBridge()
2747 	return status;  in ConfigureI2CBridge()
2753 	int status = -EINVAL;  in set_pre_saw()  local
2761 	status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);  in set_pre_saw()
2763 	if (status < 0)  in set_pre_saw()
2764 		pr_err("Error %d on %s\n", status, __func__);  in set_pre_saw()
2765 	return status;  in set_pre_saw()
2774 	int status;  in bl_direct_cmd()  local
2780 	status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);  in bl_direct_cmd()
2781 	if (status < 0)  in bl_direct_cmd()
2783 	status = write16(state, SIO_BL_TGT_HDR__A, blockbank);  in bl_direct_cmd()
2784 	if (status < 0)  in bl_direct_cmd()
2786 	status = write16(state, SIO_BL_TGT_ADDR__A, offset);  in bl_direct_cmd()
2787 	if (status < 0)  in bl_direct_cmd()
2789 	status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);  in bl_direct_cmd()
2790 	if (status < 0)  in bl_direct_cmd()
2792 	status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);  in bl_direct_cmd()
2793 	if (status < 0)  in bl_direct_cmd()
2795 	status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);  in bl_direct_cmd()
2796 	if (status < 0)  in bl_direct_cmd()
2801 		status = read16(state, SIO_BL_STATUS__A, &bl_status);  in bl_direct_cmd()
2802 		if (status < 0)  in bl_direct_cmd()
2807 		status = -EINVAL;  in bl_direct_cmd()
2811 	if (status < 0)  in bl_direct_cmd()
2812 		pr_err("Error %d on %s\n", status, __func__);  in bl_direct_cmd()
2815 	return status;  in bl_direct_cmd()
2822 	int status;  in adc_sync_measurement()  local
2827 	status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);  in adc_sync_measurement()
2828 	if (status < 0)  in adc_sync_measurement()
2830 	status = write16(state, IQM_AF_START_LOCK__A, 1);  in adc_sync_measurement()
2831 	if (status < 0)  in adc_sync_measurement()
2835 	status = read16(state, IQM_AF_PHASE0__A, &data);  in adc_sync_measurement()
2836 	if (status < 0)  in adc_sync_measurement()
2840 	status = read16(state, IQM_AF_PHASE1__A, &data);  in adc_sync_measurement()
2841 	if (status < 0)  in adc_sync_measurement()
2845 	status = read16(state, IQM_AF_PHASE2__A, &data);  in adc_sync_measurement()
2846 	if (status < 0)  in adc_sync_measurement()
2852 	if (status < 0)  in adc_sync_measurement()
2853 		pr_err("Error %d on %s\n", status, __func__);  in adc_sync_measurement()
2854 	return status;  in adc_sync_measurement()
2860 	int status;  in adc_synchronization()  local
2864 	status = adc_sync_measurement(state, &count);  in adc_synchronization()
2865 	if (status < 0)  in adc_synchronization()
2872 		status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);  in adc_synchronization()
2873 		if (status < 0)  in adc_synchronization()
2885 		status = write16(state, IQM_AF_CLKNEG__A, clk_neg);  in adc_synchronization()
2886 		if (status < 0)  in adc_synchronization()
2888 		status = adc_sync_measurement(state, &count);  in adc_synchronization()
2889 		if (status < 0)  in adc_synchronization()
2894 		status = -EINVAL;  in adc_synchronization()
2896 	if (status < 0)  in adc_synchronization()
2897 		pr_err("Error %d on %s\n", status, __func__);  in adc_synchronization()
2898 	return status;  in adc_synchronization()
2911 	int status;  in set_frequency_shifter()  local
2960 	status = write32(state, IQM_FS_RATE_OFS_LO__A,  in set_frequency_shifter()
2962 	if (status < 0)  in set_frequency_shifter()
2963 		pr_err("Error %d on %s\n", status, __func__);  in set_frequency_shifter()
2964 	return status;  in set_frequency_shifter()
2986 	int status = 0;  in init_agc()  local
3019 	status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,  in init_agc()
3021 	if (status < 0)  in init_agc()
3024 	status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);  in init_agc()
3025 	if (status < 0)  in init_agc()
3027 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);  in init_agc()
3028 	if (status < 0)  in init_agc()
3030 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);  in init_agc()
3031 	if (status < 0)  in init_agc()
3033 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);  in init_agc()
3034 	if (status < 0)  in init_agc()
3036 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,  in init_agc()
3038 	if (status < 0)  in init_agc()
3040 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,  in init_agc()
3042 	if (status < 0)  in init_agc()
3044 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);  in init_agc()
3045 	if (status < 0)  in init_agc()
3047 	status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);  in init_agc()
3048 	if (status < 0)  in init_agc()
3050 	status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);  in init_agc()
3051 	if (status < 0)  in init_agc()
3053 	status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);  in init_agc()
3054 	if (status < 0)  in init_agc()
3056 	status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);  in init_agc()
3057 	if (status < 0)  in init_agc()
3059 	status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);  in init_agc()
3060 	if (status < 0)  in init_agc()
3063 	status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,  in init_agc()
3065 	if (status < 0)  in init_agc()
3067 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,  in init_agc()
3069 	if (status < 0)  in init_agc()
3071 	status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);  in init_agc()
3072 	if (status < 0)  in init_agc()
3075 	status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);  in init_agc()
3076 	if (status < 0)  in init_agc()
3078 	status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);  in init_agc()
3079 	if (status < 0)  in init_agc()
3081 	status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);  in init_agc()
3082 	if (status < 0)  in init_agc()
3085 	status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);  in init_agc()
3086 	if (status < 0)  in init_agc()
3088 	status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);  in init_agc()
3089 	if (status < 0)  in init_agc()
3091 	status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);  in init_agc()
3092 	if (status < 0)  in init_agc()
3094 	status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);  in init_agc()
3095 	if (status < 0)  in init_agc()
3097 	status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);  in init_agc()
3098 	if (status < 0)  in init_agc()
3100 	status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);  in init_agc()
3101 	if (status < 0)  in init_agc()
3103 	status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);  in init_agc()
3104 	if (status < 0)  in init_agc()
3106 	status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);  in init_agc()
3107 	if (status < 0)  in init_agc()
3109 	status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);  in init_agc()
3110 	if (status < 0)  in init_agc()
3112 	status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);  in init_agc()
3113 	if (status < 0)  in init_agc()
3115 	status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);  in init_agc()
3116 	if (status < 0)  in init_agc()
3118 	status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);  in init_agc()
3119 	if (status < 0)  in init_agc()
3121 	status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);  in init_agc()
3122 	if (status < 0)  in init_agc()
3124 	status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);  in init_agc()
3125 	if (status < 0)  in init_agc()
3127 	status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);  in init_agc()
3128 	if (status < 0)  in init_agc()
3130 	status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);  in init_agc()
3131 	if (status < 0)  in init_agc()
3133 	status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);  in init_agc()
3134 	if (status < 0)  in init_agc()
3136 	status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);  in init_agc()
3137 	if (status < 0)  in init_agc()
3139 	status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);  in init_agc()
3140 	if (status < 0)  in init_agc()
3144 	status = read16(state, SCU_RAM_AGC_KI__A, &data);  in init_agc()
3145 	if (status < 0)  in init_agc()
3154 	status = write16(state, SCU_RAM_AGC_KI__A, data);  in init_agc()
3156 	if (status < 0)  in init_agc()
3157 		pr_err("Error %d on %s\n", status, __func__);  in init_agc()
3158 	return status;  in init_agc()
3163 	int status;  in dvbtqam_get_acc_pkt_err()  local
3167 		status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);  in dvbtqam_get_acc_pkt_err()
3169 		status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,  in dvbtqam_get_acc_pkt_err()
3171 	if (status < 0)  in dvbtqam_get_acc_pkt_err()
3172 		pr_err("Error %d on %s\n", status, __func__);  in dvbtqam_get_acc_pkt_err()
3173 	return status;  in dvbtqam_get_acc_pkt_err()
3185 	int status;  in dvbt_sc_command()  local
3188 	status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);  in dvbt_sc_command()
3191 		status = -EINVAL;  in dvbt_sc_command()
3193 	if (status < 0)  in dvbt_sc_command()
3200 		status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);  in dvbt_sc_command()
3203 	if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))  in dvbt_sc_command()
3212 		status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);  in dvbt_sc_command()
3213 		if (status < 0)  in dvbt_sc_command()
3222 	status = 0;  in dvbt_sc_command()
3231 		status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);  in dvbt_sc_command()
3235 		status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);  in dvbt_sc_command()
3240 		status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);  in dvbt_sc_command()
3244 		status = -EINVAL;  in dvbt_sc_command()
3246 	if (status < 0)  in dvbt_sc_command()
3253 		status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);  in dvbt_sc_command()
3256 	if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))  in dvbt_sc_command()
3260 	status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);  in dvbt_sc_command()
3263 		status = -EINVAL;  in dvbt_sc_command()
3265 	if (status < 0)  in dvbt_sc_command()
3277 		status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));  in dvbt_sc_command()
3289 		status = -EINVAL;  in dvbt_sc_command()
3293 	if (status < 0)  in dvbt_sc_command()
3294 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_sc_command()
3295 	return status;  in dvbt_sc_command()
3301 	int status;  in power_up_dvbt()  local
3304 	status = ctrl_power_mode(state, &power_mode);  in power_up_dvbt()
3305 	if (status < 0)  in power_up_dvbt()
3306 		pr_err("Error %d on %s\n", status, __func__);  in power_up_dvbt()
3307 	return status;  in power_up_dvbt()
3312 	int status;  in dvbt_ctrl_set_inc_enable()  local
3316 		status = write16(state, IQM_CF_BYPASSDET__A, 0);  in dvbt_ctrl_set_inc_enable()
3318 		status = write16(state, IQM_CF_BYPASSDET__A, 1);  in dvbt_ctrl_set_inc_enable()
3319 	if (status < 0)  in dvbt_ctrl_set_inc_enable()
3320 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_ctrl_set_inc_enable()
3321 	return status;  in dvbt_ctrl_set_inc_enable()
3328 	int status;  in dvbt_ctrl_set_fr_enable()  local
3333 		status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,  in dvbt_ctrl_set_fr_enable()
3337 		status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);  in dvbt_ctrl_set_fr_enable()
3339 	if (status < 0)  in dvbt_ctrl_set_fr_enable()
3340 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_ctrl_set_fr_enable()
3342 	return status;  in dvbt_ctrl_set_fr_enable()
3349 	int status;  in dvbt_ctrl_set_echo_threshold()  local
3352 	status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);  in dvbt_ctrl_set_echo_threshold()
3353 	if (status < 0)  in dvbt_ctrl_set_echo_threshold()
3373 	status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);  in dvbt_ctrl_set_echo_threshold()
3375 	if (status < 0)  in dvbt_ctrl_set_echo_threshold()
3376 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_ctrl_set_echo_threshold()
3377 	return status;  in dvbt_ctrl_set_echo_threshold()
3383 	int status = -EINVAL;  in dvbt_ctrl_set_sqi_speed()  local
3395 	status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,  in dvbt_ctrl_set_sqi_speed()
3398 	if (status < 0)  in dvbt_ctrl_set_sqi_speed()
3399 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_ctrl_set_sqi_speed()
3400 	return status;  in dvbt_ctrl_set_sqi_speed()
3415 	int status;  in dvbt_activate_presets()  local
3423 	status = dvbt_ctrl_set_inc_enable(state, &setincenable);  in dvbt_activate_presets()
3424 	if (status < 0)  in dvbt_activate_presets()
3426 	status = dvbt_ctrl_set_fr_enable(state, &setfrenable);  in dvbt_activate_presets()
3427 	if (status < 0)  in dvbt_activate_presets()
3429 	status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);  in dvbt_activate_presets()
3430 	if (status < 0)  in dvbt_activate_presets()
3432 	status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);  in dvbt_activate_presets()
3433 	if (status < 0)  in dvbt_activate_presets()
3435 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,  in dvbt_activate_presets()
3438 	if (status < 0)  in dvbt_activate_presets()
3439 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_activate_presets()
3440 	return status;  in dvbt_activate_presets()
3458 	int status;  in set_dvbt_standard()  local
3466 	status = scu_command(state,  in set_dvbt_standard()
3470 	if (status < 0)  in set_dvbt_standard()
3474 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM  in set_dvbt_standard()
3477 	if (status < 0)  in set_dvbt_standard()
3481 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);  in set_dvbt_standard()
3482 	if (status < 0)  in set_dvbt_standard()
3484 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);  in set_dvbt_standard()
3485 	if (status < 0)  in set_dvbt_standard()
3487 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);  in set_dvbt_standard()
3488 	if (status < 0)  in set_dvbt_standard()
3493 	status = write16(state, IQM_AF_UPD_SEL__A, 1);  in set_dvbt_standard()
3494 	if (status < 0)  in set_dvbt_standard()
3497 	status = write16(state, IQM_AF_CLP_LEN__A, 0);  in set_dvbt_standard()
3498 	if (status < 0)  in set_dvbt_standard()
3501 	status = write16(state, IQM_AF_SNS_LEN__A, 0);  in set_dvbt_standard()
3502 	if (status < 0)  in set_dvbt_standard()
3505 	status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);  in set_dvbt_standard()
3506 	if (status < 0)  in set_dvbt_standard()
3508 	status = set_iqm_af(state, true);  in set_dvbt_standard()
3509 	if (status < 0)  in set_dvbt_standard()
3512 	status = write16(state, IQM_AF_AGC_RF__A, 0);  in set_dvbt_standard()
3513 	if (status < 0)  in set_dvbt_standard()
3517 	status = write16(state, IQM_AF_INC_LCT__A, 0);	/* crunch in IQM_CF */  in set_dvbt_standard()
3518 	if (status < 0)  in set_dvbt_standard()
3520 	status = write16(state, IQM_CF_DET_LCT__A, 0);	/* detect in IQM_CF */  in set_dvbt_standard()
3521 	if (status < 0)  in set_dvbt_standard()
3523 	status = write16(state, IQM_CF_WND_LEN__A, 3);	/* peak detector window length */  in set_dvbt_standard()
3524 	if (status < 0)  in set_dvbt_standard()
3527 	status = write16(state, IQM_RC_STRETCH__A, 16);  in set_dvbt_standard()
3528 	if (status < 0)  in set_dvbt_standard()
3530 	status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */  in set_dvbt_standard()
3531 	if (status < 0)  in set_dvbt_standard()
3533 	status = write16(state, IQM_CF_DS_ENA__A, 0x4);	/* decimate output 2 */  in set_dvbt_standard()
3534 	if (status < 0)  in set_dvbt_standard()
3536 	status = write16(state, IQM_CF_SCALE__A, 1600);  in set_dvbt_standard()
3537 	if (status < 0)  in set_dvbt_standard()
3539 	status = write16(state, IQM_CF_SCALE_SH__A, 0);  in set_dvbt_standard()
3540 	if (status < 0)  in set_dvbt_standard()
3544 	status = write16(state, IQM_AF_CLP_TH__A, 448);  in set_dvbt_standard()
3545 	if (status < 0)  in set_dvbt_standard()
3547 	status = write16(state, IQM_CF_DATATH__A, 495);	/* crunching threshold */  in set_dvbt_standard()
3548 	if (status < 0)  in set_dvbt_standard()
3551 	status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,  in set_dvbt_standard()
3553 	if (status < 0)  in set_dvbt_standard()
3556 	status = write16(state, IQM_CF_PKDTH__A, 2);	/* peak detector threshold */  in set_dvbt_standard()
3557 	if (status < 0)  in set_dvbt_standard()
3559 	status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);  in set_dvbt_standard()
3560 	if (status < 0)  in set_dvbt_standard()
3563 	status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);  in set_dvbt_standard()
3564 	if (status < 0)  in set_dvbt_standard()
3566 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);  in set_dvbt_standard()
3567 	if (status < 0)  in set_dvbt_standard()
3571 	status = adc_synchronization(state);  in set_dvbt_standard()
3572 	if (status < 0)  in set_dvbt_standard()
3574 	status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);  in set_dvbt_standard()
3575 	if (status < 0)  in set_dvbt_standard()
3579 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_dvbt_standard()
3580 	if (status < 0)  in set_dvbt_standard()
3583 	status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);  in set_dvbt_standard()
3584 	if (status < 0)  in set_dvbt_standard()
3586 	status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);  in set_dvbt_standard()
3587 	if (status < 0)  in set_dvbt_standard()
3591 	status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);  in set_dvbt_standard()
3592 	if (status < 0)  in set_dvbt_standard()
3595 	status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);  in set_dvbt_standard()
3596 	if (status < 0)  in set_dvbt_standard()
3600 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_dvbt_standard()
3601 	if (status < 0)  in set_dvbt_standard()
3606 		status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,  in set_dvbt_standard()
3608 		if (status < 0)  in set_dvbt_standard()
3614 	status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);  in set_dvbt_standard()
3615 	if (status < 0)  in set_dvbt_standard()
3617 	status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);  in set_dvbt_standard()
3618 	if (status < 0)  in set_dvbt_standard()
3623 	status = write16(state, FEC_DI_INPUT_CTL__A, 1);	/* OFDM input */  in set_dvbt_standard()
3624 	if (status < 0)  in set_dvbt_standard()
3629 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);  in set_dvbt_standard()
3630 	if (status < 0)  in set_dvbt_standard()
3633 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);  in set_dvbt_standard()
3634 	if (status < 0)  in set_dvbt_standard()
3637 	status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);  in set_dvbt_standard()
3638 	if (status < 0)  in set_dvbt_standard()
3642 	status = mpegts_dto_setup(state, OM_DVBT);  in set_dvbt_standard()
3643 	if (status < 0)  in set_dvbt_standard()
3646 	status = dvbt_activate_presets(state);  in set_dvbt_standard()
3647 	if (status < 0)  in set_dvbt_standard()
3651 	if (status < 0)  in set_dvbt_standard()
3652 		pr_err("Error %d on %s\n", status, __func__);  in set_dvbt_standard()
3653 	return status;  in set_dvbt_standard()
3665 	int status;  in dvbt_start()  local
3672 	status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,  in dvbt_start()
3675 	if (status < 0)  in dvbt_start()
3678 	status = mpegts_start(state);  in dvbt_start()
3679 	if (status < 0)  in dvbt_start()
3681 	status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);  in dvbt_start()
3682 	if (status < 0)  in dvbt_start()
3685 	if (status < 0)  in dvbt_start()
3686 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_start()
3687 	return status;  in dvbt_start()
3707 	int status;  in set_dvbt()  local
3712 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM  in set_dvbt()
3715 	if (status < 0)  in set_dvbt()
3719 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_dvbt()
3720 	if (status < 0)  in set_dvbt()
3724 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);  in set_dvbt()
3725 	if (status < 0)  in set_dvbt()
3727 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);  in set_dvbt()
3728 	if (status < 0)  in set_dvbt()
3733 	status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);  in set_dvbt()
3734 	if (status < 0)  in set_dvbt()
3816 		status = -EINVAL;  in set_dvbt()
3822 	status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);  in set_dvbt()
3823 	if (status < 0)  in set_dvbt()
3867 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,  in set_dvbt()
3869 		if (status < 0)  in set_dvbt()
3872 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,  in set_dvbt()
3874 		if (status < 0)  in set_dvbt()
3876 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,  in set_dvbt()
3878 		if (status < 0)  in set_dvbt()
3880 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,  in set_dvbt()
3882 		if (status < 0)  in set_dvbt()
3884 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,  in set_dvbt()
3886 		if (status < 0)  in set_dvbt()
3891 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,  in set_dvbt()
3893 		if (status < 0)  in set_dvbt()
3896 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,  in set_dvbt()
3898 		if (status < 0)  in set_dvbt()
3900 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,  in set_dvbt()
3902 		if (status < 0)  in set_dvbt()
3904 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,  in set_dvbt()
3906 		if (status < 0)  in set_dvbt()
3908 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,  in set_dvbt()
3910 		if (status < 0)  in set_dvbt()
3915 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,  in set_dvbt()
3917 		if (status < 0)  in set_dvbt()
3920 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,  in set_dvbt()
3922 		if (status < 0)  in set_dvbt()
3924 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,  in set_dvbt()
3926 		if (status < 0)  in set_dvbt()
3928 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,  in set_dvbt()
3930 		if (status < 0)  in set_dvbt()
3932 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,  in set_dvbt()
3934 		if (status < 0)  in set_dvbt()
3938 		status = -EINVAL;  in set_dvbt()
3969 	status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);  in set_dvbt()
3970 	if (status < 0)  in set_dvbt()
3976 	status = dvbt_set_frequency_shift(demod, channel, tuner_offset);  in set_dvbt()
3977 	if (status < 0)  in set_dvbt()
3980 	status = set_frequency_shifter(state, intermediate_freqk_hz,  in set_dvbt()
3982 	if (status < 0)  in set_dvbt()
3988 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_dvbt()
3989 	if (status < 0)  in set_dvbt()
3993 	status = write16(state, OFDM_SC_COMM_STATE__A, 0);  in set_dvbt()
3994 	if (status < 0)  in set_dvbt()
3996 	status = write16(state, OFDM_SC_COMM_EXEC__A, 1);  in set_dvbt()
3997 	if (status < 0)  in set_dvbt()
4001 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM  in set_dvbt()
4004 	if (status < 0)  in set_dvbt()
4013 	status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,  in set_dvbt()
4015 	if (status < 0)  in set_dvbt()
4019 		status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);  in set_dvbt()
4021 	if (status < 0)  in set_dvbt()
4022 		pr_err("Error %d on %s\n", status, __func__);  in set_dvbt()
4024 	return status;  in set_dvbt()
4039 	int status;  in get_dvbt_lock_status()  local
4053 	status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);  in get_dvbt_lock_status()
4054 	if (status < 0)  in get_dvbt_lock_status()
4059 	status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);  in get_dvbt_lock_status()
4060 	if (status < 0)  in get_dvbt_lock_status()
4072 	if (status < 0)  in get_dvbt_lock_status()
4073 		pr_err("Error %d on %s\n", status, __func__);  in get_dvbt_lock_status()
4075 	return status;  in get_dvbt_lock_status()
4081 	int status;  in power_up_qam()  local
4084 	status = ctrl_power_mode(state, &power_mode);  in power_up_qam()
4085 	if (status < 0)  in power_up_qam()
4086 		pr_err("Error %d on %s\n", status, __func__);  in power_up_qam()
4088 	return status;  in power_up_qam()
4097 	int status = 0;  in power_down_qam()  local
4100 	status = read16(state, SCU_COMM_EXEC__A, &data);  in power_down_qam()
4101 	if (status < 0)  in power_down_qam()
4109 		status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);  in power_down_qam()
4110 		if (status < 0)  in power_down_qam()
4112 		status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM  in power_down_qam()
4115 		if (status < 0)  in power_down_qam()
4119 	status = set_iqm_af(state, false);  in power_down_qam()
4122 	if (status < 0)  in power_down_qam()
4123 		pr_err("Error %d on %s\n", status, __func__);  in power_down_qam()
4125 	return status;  in power_down_qam()
4149 	int status = 0;  in set_qam_measurement()  local
4177 		status = -EINVAL;  in set_qam_measurement()
4179 	if (status < 0)  in set_qam_measurement()
4193 		status = -EINVAL;  in set_qam_measurement()
4194 		if (status < 0)  in set_qam_measurement()
4202 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);  in set_qam_measurement()
4203 	if (status < 0)  in set_qam_measurement()
4205 	status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,  in set_qam_measurement()
4207 	if (status < 0)  in set_qam_measurement()
4209 	status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);  in set_qam_measurement()
4211 	if (status < 0)  in set_qam_measurement()
4212 		pr_err("Error %d on %s\n", status, __func__);  in set_qam_measurement()
4213 	return status;  in set_qam_measurement()
4218 	int status = 0;  in set_qam16()  local
4223 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);  in set_qam16()
4224 	if (status < 0)  in set_qam16()
4226 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);  in set_qam16()
4227 	if (status < 0)  in set_qam16()
4229 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);  in set_qam16()
4230 	if (status < 0)  in set_qam16()
4232 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);  in set_qam16()
4233 	if (status < 0)  in set_qam16()
4235 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);  in set_qam16()
4236 	if (status < 0)  in set_qam16()
4238 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);  in set_qam16()
4239 	if (status < 0)  in set_qam16()
4242 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);  in set_qam16()
4243 	if (status < 0)  in set_qam16()
4245 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);  in set_qam16()
4246 	if (status < 0)  in set_qam16()
4248 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);  in set_qam16()
4249 	if (status < 0)  in set_qam16()
4251 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);  in set_qam16()
4252 	if (status < 0)  in set_qam16()
4254 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);  in set_qam16()
4255 	if (status < 0)  in set_qam16()
4257 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam16()
4258 	if (status < 0)  in set_qam16()
4261 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);  in set_qam16()
4262 	if (status < 0)  in set_qam16()
4264 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);  in set_qam16()
4265 	if (status < 0)  in set_qam16()
4267 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam16()
4268 	if (status < 0)  in set_qam16()
4272 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam16()
4274 	if (status < 0)  in set_qam16()
4278 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam16()
4279 	if (status < 0)  in set_qam16()
4281 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam16()
4282 	if (status < 0)  in set_qam16()
4284 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam16()
4285 	if (status < 0)  in set_qam16()
4287 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam16()
4288 	if (status < 0)  in set_qam16()
4290 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam16()
4291 	if (status < 0)  in set_qam16()
4293 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam16()
4294 	if (status < 0)  in set_qam16()
4296 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam16()
4297 	if (status < 0)  in set_qam16()
4299 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam16()
4300 	if (status < 0)  in set_qam16()
4303 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam16()
4304 	if (status < 0)  in set_qam16()
4306 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);  in set_qam16()
4307 	if (status < 0)  in set_qam16()
4309 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);  in set_qam16()
4310 	if (status < 0)  in set_qam16()
4312 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam16()
4313 	if (status < 0)  in set_qam16()
4315 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);  in set_qam16()
4316 	if (status < 0)  in set_qam16()
4318 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);  in set_qam16()
4319 	if (status < 0)  in set_qam16()
4321 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam16()
4322 	if (status < 0)  in set_qam16()
4324 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);  in set_qam16()
4325 	if (status < 0)  in set_qam16()
4327 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);  in set_qam16()
4328 	if (status < 0)  in set_qam16()
4330 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam16()
4331 	if (status < 0)  in set_qam16()
4333 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam16()
4334 	if (status < 0)  in set_qam16()
4336 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);  in set_qam16()
4337 	if (status < 0)  in set_qam16()
4343 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);  in set_qam16()
4344 	if (status < 0)  in set_qam16()
4346 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);  in set_qam16()
4347 	if (status < 0)  in set_qam16()
4349 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);  in set_qam16()
4350 	if (status < 0)  in set_qam16()
4352 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);  in set_qam16()
4353 	if (status < 0)  in set_qam16()
4355 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);  in set_qam16()
4356 	if (status < 0)  in set_qam16()
4358 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);  in set_qam16()
4359 	if (status < 0)  in set_qam16()
4362 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam16()
4363 	if (status < 0)  in set_qam16()
4365 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam16()
4366 	if (status < 0)  in set_qam16()
4368 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);  in set_qam16()
4369 	if (status < 0)  in set_qam16()
4375 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);  in set_qam16()
4376 	if (status < 0)  in set_qam16()
4378 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);  in set_qam16()
4379 	if (status < 0)  in set_qam16()
4381 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);  in set_qam16()
4382 	if (status < 0)  in set_qam16()
4384 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);  in set_qam16()
4385 	if (status < 0)  in set_qam16()
4387 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);  in set_qam16()
4388 	if (status < 0)  in set_qam16()
4390 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);  in set_qam16()
4391 	if (status < 0)  in set_qam16()
4393 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);  in set_qam16()
4394 	if (status < 0)  in set_qam16()
4398 	if (status < 0)  in set_qam16()
4399 		pr_err("Error %d on %s\n", status, __func__);  in set_qam16()
4400 	return status;  in set_qam16()
4412 	int status = 0;  in set_qam32()  local
4418 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);  in set_qam32()
4419 	if (status < 0)  in set_qam32()
4421 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);  in set_qam32()
4422 	if (status < 0)  in set_qam32()
4424 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);  in set_qam32()
4425 	if (status < 0)  in set_qam32()
4427 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);  in set_qam32()
4428 	if (status < 0)  in set_qam32()
4430 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);  in set_qam32()
4431 	if (status < 0)  in set_qam32()
4433 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);  in set_qam32()
4434 	if (status < 0)  in set_qam32()
4438 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);  in set_qam32()
4439 	if (status < 0)  in set_qam32()
4441 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);  in set_qam32()
4442 	if (status < 0)  in set_qam32()
4444 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);  in set_qam32()
4445 	if (status < 0)  in set_qam32()
4447 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);  in set_qam32()
4448 	if (status < 0)  in set_qam32()
4450 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);  in set_qam32()
4451 	if (status < 0)  in set_qam32()
4453 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam32()
4454 	if (status < 0)  in set_qam32()
4457 	status = write16(state, QAM_SY_SYNC_HWM__A, 6);  in set_qam32()
4458 	if (status < 0)  in set_qam32()
4460 	status = write16(state, QAM_SY_SYNC_AWM__A, 5);  in set_qam32()
4461 	if (status < 0)  in set_qam32()
4463 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam32()
4464 	if (status < 0)  in set_qam32()
4469 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam32()
4471 	if (status < 0)  in set_qam32()
4477 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam32()
4478 	if (status < 0)  in set_qam32()
4480 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam32()
4481 	if (status < 0)  in set_qam32()
4483 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam32()
4484 	if (status < 0)  in set_qam32()
4486 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam32()
4487 	if (status < 0)  in set_qam32()
4489 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam32()
4490 	if (status < 0)  in set_qam32()
4492 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam32()
4493 	if (status < 0)  in set_qam32()
4495 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam32()
4496 	if (status < 0)  in set_qam32()
4498 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam32()
4499 	if (status < 0)  in set_qam32()
4502 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam32()
4503 	if (status < 0)  in set_qam32()
4505 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);  in set_qam32()
4506 	if (status < 0)  in set_qam32()
4508 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);  in set_qam32()
4509 	if (status < 0)  in set_qam32()
4511 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam32()
4512 	if (status < 0)  in set_qam32()
4514 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);  in set_qam32()
4515 	if (status < 0)  in set_qam32()
4517 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);  in set_qam32()
4518 	if (status < 0)  in set_qam32()
4520 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam32()
4521 	if (status < 0)  in set_qam32()
4523 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);  in set_qam32()
4524 	if (status < 0)  in set_qam32()
4526 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);  in set_qam32()
4527 	if (status < 0)  in set_qam32()
4529 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam32()
4530 	if (status < 0)  in set_qam32()
4532 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam32()
4533 	if (status < 0)  in set_qam32()
4535 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);  in set_qam32()
4536 	if (status < 0)  in set_qam32()
4542 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);  in set_qam32()
4543 	if (status < 0)  in set_qam32()
4545 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);  in set_qam32()
4546 	if (status < 0)  in set_qam32()
4548 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam32()
4549 	if (status < 0)  in set_qam32()
4551 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);  in set_qam32()
4552 	if (status < 0)  in set_qam32()
4554 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);  in set_qam32()
4555 	if (status < 0)  in set_qam32()
4557 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);  in set_qam32()
4558 	if (status < 0)  in set_qam32()
4561 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam32()
4562 	if (status < 0)  in set_qam32()
4564 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam32()
4565 	if (status < 0)  in set_qam32()
4567 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);  in set_qam32()
4568 	if (status < 0)  in set_qam32()
4574 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);  in set_qam32()
4575 	if (status < 0)  in set_qam32()
4577 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);  in set_qam32()
4578 	if (status < 0)  in set_qam32()
4580 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);  in set_qam32()
4581 	if (status < 0)  in set_qam32()
4583 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);  in set_qam32()
4584 	if (status < 0)  in set_qam32()
4586 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);  in set_qam32()
4587 	if (status < 0)  in set_qam32()
4589 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);  in set_qam32()
4590 	if (status < 0)  in set_qam32()
4592 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);  in set_qam32()
4594 	if (status < 0)  in set_qam32()
4595 		pr_err("Error %d on %s\n", status, __func__);  in set_qam32()
4596 	return status;  in set_qam32()
4608 	int status = 0;  in set_qam64()  local
4613 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);  in set_qam64()
4614 	if (status < 0)  in set_qam64()
4616 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);  in set_qam64()
4617 	if (status < 0)  in set_qam64()
4619 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);  in set_qam64()
4620 	if (status < 0)  in set_qam64()
4622 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);  in set_qam64()
4623 	if (status < 0)  in set_qam64()
4625 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);  in set_qam64()
4626 	if (status < 0)  in set_qam64()
4628 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);  in set_qam64()
4629 	if (status < 0)  in set_qam64()
4633 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);  in set_qam64()
4634 	if (status < 0)  in set_qam64()
4636 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);  in set_qam64()
4637 	if (status < 0)  in set_qam64()
4639 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);  in set_qam64()
4640 	if (status < 0)  in set_qam64()
4642 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);  in set_qam64()
4643 	if (status < 0)  in set_qam64()
4645 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);  in set_qam64()
4646 	if (status < 0)  in set_qam64()
4648 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam64()
4649 	if (status < 0)  in set_qam64()
4652 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);  in set_qam64()
4653 	if (status < 0)  in set_qam64()
4655 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);  in set_qam64()
4656 	if (status < 0)  in set_qam64()
4658 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam64()
4659 	if (status < 0)  in set_qam64()
4663 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam64()
4665 	if (status < 0)  in set_qam64()
4671 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam64()
4672 	if (status < 0)  in set_qam64()
4674 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam64()
4675 	if (status < 0)  in set_qam64()
4677 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam64()
4678 	if (status < 0)  in set_qam64()
4680 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam64()
4681 	if (status < 0)  in set_qam64()
4683 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam64()
4684 	if (status < 0)  in set_qam64()
4686 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam64()
4687 	if (status < 0)  in set_qam64()
4689 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam64()
4690 	if (status < 0)  in set_qam64()
4692 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam64()
4693 	if (status < 0)  in set_qam64()
4696 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam64()
4697 	if (status < 0)  in set_qam64()
4699 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);  in set_qam64()
4700 	if (status < 0)  in set_qam64()
4702 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);  in set_qam64()
4703 	if (status < 0)  in set_qam64()
4705 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam64()
4706 	if (status < 0)  in set_qam64()
4708 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);  in set_qam64()
4709 	if (status < 0)  in set_qam64()
4711 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);  in set_qam64()
4712 	if (status < 0)  in set_qam64()
4714 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam64()
4715 	if (status < 0)  in set_qam64()
4717 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);  in set_qam64()
4718 	if (status < 0)  in set_qam64()
4720 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);  in set_qam64()
4721 	if (status < 0)  in set_qam64()
4723 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam64()
4724 	if (status < 0)  in set_qam64()
4726 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam64()
4727 	if (status < 0)  in set_qam64()
4729 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);  in set_qam64()
4730 	if (status < 0)  in set_qam64()
4736 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);  in set_qam64()
4737 	if (status < 0)  in set_qam64()
4739 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);  in set_qam64()
4740 	if (status < 0)  in set_qam64()
4742 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam64()
4743 	if (status < 0)  in set_qam64()
4745 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);  in set_qam64()
4746 	if (status < 0)  in set_qam64()
4748 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);  in set_qam64()
4749 	if (status < 0)  in set_qam64()
4751 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);  in set_qam64()
4752 	if (status < 0)  in set_qam64()
4755 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam64()
4756 	if (status < 0)  in set_qam64()
4758 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam64()
4759 	if (status < 0)  in set_qam64()
4761 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);  in set_qam64()
4762 	if (status < 0)  in set_qam64()
4768 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);  in set_qam64()
4769 	if (status < 0)  in set_qam64()
4771 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);  in set_qam64()
4772 	if (status < 0)  in set_qam64()
4774 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);  in set_qam64()
4775 	if (status < 0)  in set_qam64()
4777 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);  in set_qam64()
4778 	if (status < 0)  in set_qam64()
4780 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);  in set_qam64()
4781 	if (status < 0)  in set_qam64()
4783 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);  in set_qam64()
4784 	if (status < 0)  in set_qam64()
4786 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);  in set_qam64()
4788 	if (status < 0)  in set_qam64()
4789 		pr_err("Error %d on %s\n", status, __func__);  in set_qam64()
4791 	return status;  in set_qam64()
4803 	int status = 0;  in set_qam128()  local
4808 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);  in set_qam128()
4809 	if (status < 0)  in set_qam128()
4811 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);  in set_qam128()
4812 	if (status < 0)  in set_qam128()
4814 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);  in set_qam128()
4815 	if (status < 0)  in set_qam128()
4817 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);  in set_qam128()
4818 	if (status < 0)  in set_qam128()
4820 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);  in set_qam128()
4821 	if (status < 0)  in set_qam128()
4823 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);  in set_qam128()
4824 	if (status < 0)  in set_qam128()
4828 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);  in set_qam128()
4829 	if (status < 0)  in set_qam128()
4831 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);  in set_qam128()
4832 	if (status < 0)  in set_qam128()
4834 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);  in set_qam128()
4835 	if (status < 0)  in set_qam128()
4837 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);  in set_qam128()
4838 	if (status < 0)  in set_qam128()
4840 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);  in set_qam128()
4841 	if (status < 0)  in set_qam128()
4843 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam128()
4844 	if (status < 0)  in set_qam128()
4847 	status = write16(state, QAM_SY_SYNC_HWM__A, 6);  in set_qam128()
4848 	if (status < 0)  in set_qam128()
4850 	status = write16(state, QAM_SY_SYNC_AWM__A, 5);  in set_qam128()
4851 	if (status < 0)  in set_qam128()
4853 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam128()
4854 	if (status < 0)  in set_qam128()
4860 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam128()
4862 	if (status < 0)  in set_qam128()
4868 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam128()
4869 	if (status < 0)  in set_qam128()
4871 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam128()
4872 	if (status < 0)  in set_qam128()
4874 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam128()
4875 	if (status < 0)  in set_qam128()
4877 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam128()
4878 	if (status < 0)  in set_qam128()
4880 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam128()
4881 	if (status < 0)  in set_qam128()
4883 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam128()
4884 	if (status < 0)  in set_qam128()
4886 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam128()
4887 	if (status < 0)  in set_qam128()
4889 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam128()
4890 	if (status < 0)  in set_qam128()
4893 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam128()
4894 	if (status < 0)  in set_qam128()
4896 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);  in set_qam128()
4897 	if (status < 0)  in set_qam128()
4899 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);  in set_qam128()
4900 	if (status < 0)  in set_qam128()
4902 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam128()
4903 	if (status < 0)  in set_qam128()
4905 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);  in set_qam128()
4906 	if (status < 0)  in set_qam128()
4908 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);  in set_qam128()
4909 	if (status < 0)  in set_qam128()
4911 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam128()
4912 	if (status < 0)  in set_qam128()
4914 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);  in set_qam128()
4915 	if (status < 0)  in set_qam128()
4917 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);  in set_qam128()
4918 	if (status < 0)  in set_qam128()
4920 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam128()
4921 	if (status < 0)  in set_qam128()
4923 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam128()
4924 	if (status < 0)  in set_qam128()
4926 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);  in set_qam128()
4927 	if (status < 0)  in set_qam128()
4933 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);  in set_qam128()
4934 	if (status < 0)  in set_qam128()
4936 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);  in set_qam128()
4937 	if (status < 0)  in set_qam128()
4939 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam128()
4940 	if (status < 0)  in set_qam128()
4942 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);  in set_qam128()
4943 	if (status < 0)  in set_qam128()
4945 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);  in set_qam128()
4946 	if (status < 0)  in set_qam128()
4948 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);  in set_qam128()
4949 	if (status < 0)  in set_qam128()
4952 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam128()
4953 	if (status < 0)  in set_qam128()
4955 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);  in set_qam128()
4956 	if (status < 0)  in set_qam128()
4959 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);  in set_qam128()
4960 	if (status < 0)  in set_qam128()
4965 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);  in set_qam128()
4966 	if (status < 0)  in set_qam128()
4968 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);  in set_qam128()
4969 	if (status < 0)  in set_qam128()
4971 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);  in set_qam128()
4972 	if (status < 0)  in set_qam128()
4974 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);  in set_qam128()
4975 	if (status < 0)  in set_qam128()
4977 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);  in set_qam128()
4978 	if (status < 0)  in set_qam128()
4980 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);  in set_qam128()
4981 	if (status < 0)  in set_qam128()
4983 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);  in set_qam128()
4985 	if (status < 0)  in set_qam128()
4986 		pr_err("Error %d on %s\n", status, __func__);  in set_qam128()
4988 	return status;  in set_qam128()
5000 	int status = 0;  in set_qam256()  local
5005 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);  in set_qam256()
5006 	if (status < 0)  in set_qam256()
5008 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);  in set_qam256()
5009 	if (status < 0)  in set_qam256()
5011 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);  in set_qam256()
5012 	if (status < 0)  in set_qam256()
5014 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);  in set_qam256()
5015 	if (status < 0)  in set_qam256()
5017 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);  in set_qam256()
5018 	if (status < 0)  in set_qam256()
5020 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);  in set_qam256()
5021 	if (status < 0)  in set_qam256()
5025 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);  in set_qam256()
5026 	if (status < 0)  in set_qam256()
5028 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);  in set_qam256()
5029 	if (status < 0)  in set_qam256()
5031 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);  in set_qam256()
5032 	if (status < 0)  in set_qam256()
5034 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);  in set_qam256()
5035 	if (status < 0)  in set_qam256()
5037 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);  in set_qam256()
5038 	if (status < 0)  in set_qam256()
5040 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam256()
5041 	if (status < 0)  in set_qam256()
5044 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);  in set_qam256()
5045 	if (status < 0)  in set_qam256()
5047 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);  in set_qam256()
5048 	if (status < 0)  in set_qam256()
5050 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam256()
5051 	if (status < 0)  in set_qam256()
5056 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam256()
5058 	if (status < 0)  in set_qam256()
5064 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam256()
5065 	if (status < 0)  in set_qam256()
5067 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam256()
5068 	if (status < 0)  in set_qam256()
5070 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam256()
5071 	if (status < 0)  in set_qam256()
5073 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam256()
5074 	if (status < 0)  in set_qam256()
5076 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam256()
5077 	if (status < 0)  in set_qam256()
5079 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam256()
5080 	if (status < 0)  in set_qam256()
5082 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam256()
5083 	if (status < 0)  in set_qam256()
5085 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam256()
5086 	if (status < 0)  in set_qam256()
5089 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam256()
5090 	if (status < 0)  in set_qam256()
5092 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);  in set_qam256()
5093 	if (status < 0)  in set_qam256()
5095 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);  in set_qam256()
5096 	if (status < 0)  in set_qam256()
5098 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam256()
5099 	if (status < 0)  in set_qam256()
5101 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);  in set_qam256()
5102 	if (status < 0)  in set_qam256()
5104 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);  in set_qam256()
5105 	if (status < 0)  in set_qam256()
5107 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam256()
5108 	if (status < 0)  in set_qam256()
5110 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);  in set_qam256()
5111 	if (status < 0)  in set_qam256()
5113 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);  in set_qam256()
5114 	if (status < 0)  in set_qam256()
5116 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam256()
5117 	if (status < 0)  in set_qam256()
5119 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam256()
5120 	if (status < 0)  in set_qam256()
5122 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);  in set_qam256()
5123 	if (status < 0)  in set_qam256()
5129 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);  in set_qam256()
5130 	if (status < 0)  in set_qam256()
5132 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);  in set_qam256()
5133 	if (status < 0)  in set_qam256()
5135 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam256()
5136 	if (status < 0)  in set_qam256()
5138 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);  in set_qam256()
5139 	if (status < 0)  in set_qam256()
5141 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);  in set_qam256()
5142 	if (status < 0)  in set_qam256()
5144 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);  in set_qam256()
5145 	if (status < 0)  in set_qam256()
5148 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam256()
5149 	if (status < 0)  in set_qam256()
5151 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam256()
5152 	if (status < 0)  in set_qam256()
5154 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);  in set_qam256()
5155 	if (status < 0)  in set_qam256()
5161 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);  in set_qam256()
5162 	if (status < 0)  in set_qam256()
5164 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);  in set_qam256()
5165 	if (status < 0)  in set_qam256()
5167 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);  in set_qam256()
5168 	if (status < 0)  in set_qam256()
5170 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);  in set_qam256()
5171 	if (status < 0)  in set_qam256()
5173 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);  in set_qam256()
5174 	if (status < 0)  in set_qam256()
5176 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);  in set_qam256()
5177 	if (status < 0)  in set_qam256()
5179 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);  in set_qam256()
5181 	if (status < 0)  in set_qam256()
5182 		pr_err("Error %d on %s\n", status, __func__);  in set_qam256()
5183 	return status;  in set_qam256()
5196 	int status;  in qam_reset_qam()  local
5201 	status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);  in qam_reset_qam()
5202 	if (status < 0)  in qam_reset_qam()
5205 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM  in qam_reset_qam()
5209 	if (status < 0)  in qam_reset_qam()
5210 		pr_err("Error %d on %s\n", status, __func__);  in qam_reset_qam()
5211 	return status;  in qam_reset_qam()
5229 	int status;  in qam_set_symbolrate()  local
5241 	status = write16(state, IQM_FD_RATESEL__A, ratesel);  in qam_set_symbolrate()
5242 	if (status < 0)  in qam_set_symbolrate()
5251 		status = -EINVAL;  in qam_set_symbolrate()
5257 	status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);  in qam_set_symbolrate()
5258 	if (status < 0)  in qam_set_symbolrate()
5267 		status = -EINVAL;  in qam_set_symbolrate()
5275 	status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);  in qam_set_symbolrate()
5278 	if (status < 0)  in qam_set_symbolrate()
5279 		pr_err("Error %d on %s\n", status, __func__);  in qam_set_symbolrate()
5280 	return status;  in qam_set_symbolrate()
5294 	int status;  in get_qam_lock_status()  local
5299 	status = scu_command(state,  in get_qam_lock_status()
5303 	if (status < 0)  in get_qam_lock_status()
5304 		pr_err("Error %d on %s\n", status, __func__);  in get_qam_lock_status()
5323 	return status;  in get_qam_lock_status()
5336 	int status;  in qam_demodulator_command()  local
5351 		status = scu_command(state,  in qam_demodulator_command()
5355 		if (status < 0)  in qam_demodulator_command()
5358 		status = scu_command(state,  in qam_demodulator_command()
5374 		status = scu_command(state,  in qam_demodulator_command()
5382 		status = -EINVAL;  in qam_demodulator_command()
5386 	if (status < 0)  in qam_demodulator_command()
5387 		pr_warn("Warning %d on %s\n", status, __func__);  in qam_demodulator_command()
5388 	return status;  in qam_demodulator_command()
5394 	int status;  in set_qam()  local
5405 	status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);  in set_qam()
5406 	if (status < 0)  in set_qam()
5408 	status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);  in set_qam()
5409 	if (status < 0)  in set_qam()
5411 	status = qam_reset_qam(state);  in set_qam()
5412 	if (status < 0)  in set_qam()
5420 	status = qam_set_symbolrate(state);  in set_qam()
5421 	if (status < 0)  in set_qam()
5443 		status = -EINVAL;  in set_qam()
5446 	if (status < 0)  in set_qam()
5454 		status = qam_demodulator_command(state, qam_demod_param_count);  in set_qam()
5461 		|| (!state->qam_demod_parameter_count && status < 0)) {  in set_qam()
5463 		status = qam_demodulator_command(state, qam_demod_param_count);  in set_qam()
5466 	if (status < 0) {  in set_qam()
5490 	status = set_frequency(channel, tuner_freq_offset));  in set_qam()
5491 	if (status < 0)  in set_qam()
5494 	status = set_frequency_shifter(state, intermediate_freqk_hz,  in set_qam()
5496 	if (status < 0)  in set_qam()
5500 	status = set_qam_measurement(state, state->m_constellation,  in set_qam()
5502 	if (status < 0)  in set_qam()
5506 	status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);  in set_qam()
5507 	if (status < 0)  in set_qam()
5509 	status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);  in set_qam()
5510 	if (status < 0)  in set_qam()
5514 	status = write16(state, QAM_LC_RATE_LIMIT__A, 3);  in set_qam()
5515 	if (status < 0)  in set_qam()
5517 	status = write16(state, QAM_LC_LPF_FACTORP__A, 4);  in set_qam()
5518 	if (status < 0)  in set_qam()
5520 	status = write16(state, QAM_LC_LPF_FACTORI__A, 4);  in set_qam()
5521 	if (status < 0)  in set_qam()
5523 	status = write16(state, QAM_LC_MODE__A, 7);  in set_qam()
5524 	if (status < 0)  in set_qam()
5527 	status = write16(state, QAM_LC_QUAL_TAB0__A, 1);  in set_qam()
5528 	if (status < 0)  in set_qam()
5530 	status = write16(state, QAM_LC_QUAL_TAB1__A, 1);  in set_qam()
5531 	if (status < 0)  in set_qam()
5533 	status = write16(state, QAM_LC_QUAL_TAB2__A, 1);  in set_qam()
5534 	if (status < 0)  in set_qam()
5536 	status = write16(state, QAM_LC_QUAL_TAB3__A, 1);  in set_qam()
5537 	if (status < 0)  in set_qam()
5539 	status = write16(state, QAM_LC_QUAL_TAB4__A, 2);  in set_qam()
5540 	if (status < 0)  in set_qam()
5542 	status = write16(state, QAM_LC_QUAL_TAB5__A, 2);  in set_qam()
5543 	if (status < 0)  in set_qam()
5545 	status = write16(state, QAM_LC_QUAL_TAB6__A, 2);  in set_qam()
5546 	if (status < 0)  in set_qam()
5548 	status = write16(state, QAM_LC_QUAL_TAB8__A, 2);  in set_qam()
5549 	if (status < 0)  in set_qam()
5551 	status = write16(state, QAM_LC_QUAL_TAB9__A, 2);  in set_qam()
5552 	if (status < 0)  in set_qam()
5554 	status = write16(state, QAM_LC_QUAL_TAB10__A, 2);  in set_qam()
5555 	if (status < 0)  in set_qam()
5557 	status = write16(state, QAM_LC_QUAL_TAB12__A, 2);  in set_qam()
5558 	if (status < 0)  in set_qam()
5560 	status = write16(state, QAM_LC_QUAL_TAB15__A, 3);  in set_qam()
5561 	if (status < 0)  in set_qam()
5563 	status = write16(state, QAM_LC_QUAL_TAB16__A, 3);  in set_qam()
5564 	if (status < 0)  in set_qam()
5566 	status = write16(state, QAM_LC_QUAL_TAB20__A, 4);  in set_qam()
5567 	if (status < 0)  in set_qam()
5569 	status = write16(state, QAM_LC_QUAL_TAB25__A, 4);  in set_qam()
5570 	if (status < 0)  in set_qam()
5574 	status = write16(state, QAM_SY_SP_INV__A,  in set_qam()
5576 	if (status < 0)  in set_qam()
5580 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_qam()
5581 	if (status < 0)  in set_qam()
5587 		status = set_qam16(state);  in set_qam()
5590 		status = set_qam32(state);  in set_qam()
5594 		status = set_qam64(state);  in set_qam()
5597 		status = set_qam128(state);  in set_qam()
5600 		status = set_qam256(state);  in set_qam()
5603 		status = -EINVAL;  in set_qam()
5606 	if (status < 0)  in set_qam()
5610 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_qam()
5611 	if (status < 0)  in set_qam()
5617 	status = mpegts_dto_setup(state, state->m_operation_mode);  in set_qam()
5618 	if (status < 0)  in set_qam()
5622 	status = mpegts_start(state);  in set_qam()
5623 	if (status < 0)  in set_qam()
5625 	status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);  in set_qam()
5626 	if (status < 0)  in set_qam()
5628 	status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);  in set_qam()
5629 	if (status < 0)  in set_qam()
5631 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);  in set_qam()
5632 	if (status < 0)  in set_qam()
5636 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM  in set_qam()
5639 	if (status < 0)  in set_qam()
5646 	if (status < 0)  in set_qam()
5647 		pr_err("Error %d on %s\n", status, __func__);  in set_qam()
5648 	return status;  in set_qam()
5654 	int status;  in set_qam_standard()  local
5667 	status = power_up_qam(state);  in set_qam_standard()
5668 	if (status < 0)  in set_qam_standard()
5671 	status = qam_reset_qam(state);  in set_qam_standard()
5672 	if (status < 0)  in set_qam_standard()
5677 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);  in set_qam_standard()
5678 	if (status < 0)  in set_qam_standard()
5680 	status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);  in set_qam_standard()
5681 	if (status < 0)  in set_qam_standard()
5688 		status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,  in set_qam_standard()
5693 		status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,  in set_qam_standard()
5697 		if (status < 0)  in set_qam_standard()
5699 		status = bl_direct_cmd(state,  in set_qam_standard()
5706 		status = -EINVAL;  in set_qam_standard()
5708 	if (status < 0)  in set_qam_standard()
5711 	status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);  in set_qam_standard()
5712 	if (status < 0)  in set_qam_standard()
5714 	status = write16(state, IQM_CF_SYMMETRIC__A, 0);  in set_qam_standard()
5715 	if (status < 0)  in set_qam_standard()
5717 	status = write16(state, IQM_CF_MIDTAP__A,  in set_qam_standard()
5719 	if (status < 0)  in set_qam_standard()
5722 	status = write16(state, IQM_RC_STRETCH__A, 21);  in set_qam_standard()
5723 	if (status < 0)  in set_qam_standard()
5725 	status = write16(state, IQM_AF_CLP_LEN__A, 0);  in set_qam_standard()
5726 	if (status < 0)  in set_qam_standard()
5728 	status = write16(state, IQM_AF_CLP_TH__A, 448);  in set_qam_standard()
5729 	if (status < 0)  in set_qam_standard()
5731 	status = write16(state, IQM_AF_SNS_LEN__A, 0);  in set_qam_standard()
5732 	if (status < 0)  in set_qam_standard()
5734 	status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);  in set_qam_standard()
5735 	if (status < 0)  in set_qam_standard()
5738 	status = write16(state, IQM_FS_ADJ_SEL__A, 1);  in set_qam_standard()
5739 	if (status < 0)  in set_qam_standard()
5741 	status = write16(state, IQM_RC_ADJ_SEL__A, 1);  in set_qam_standard()
5742 	if (status < 0)  in set_qam_standard()
5744 	status = write16(state, IQM_CF_ADJ_SEL__A, 1);  in set_qam_standard()
5745 	if (status < 0)  in set_qam_standard()
5747 	status = write16(state, IQM_AF_UPD_SEL__A, 0);  in set_qam_standard()
5748 	if (status < 0)  in set_qam_standard()
5752 	status = write16(state, IQM_CF_CLP_VAL__A, 500);  in set_qam_standard()
5753 	if (status < 0)  in set_qam_standard()
5755 	status = write16(state, IQM_CF_DATATH__A, 1000);  in set_qam_standard()
5756 	if (status < 0)  in set_qam_standard()
5758 	status = write16(state, IQM_CF_BYPASSDET__A, 1);  in set_qam_standard()
5759 	if (status < 0)  in set_qam_standard()
5761 	status = write16(state, IQM_CF_DET_LCT__A, 0);  in set_qam_standard()
5762 	if (status < 0)  in set_qam_standard()
5764 	status = write16(state, IQM_CF_WND_LEN__A, 1);  in set_qam_standard()
5765 	if (status < 0)  in set_qam_standard()
5767 	status = write16(state, IQM_CF_PKDTH__A, 1);  in set_qam_standard()
5768 	if (status < 0)  in set_qam_standard()
5770 	status = write16(state, IQM_AF_INC_BYPASS__A, 1);  in set_qam_standard()
5771 	if (status < 0)  in set_qam_standard()
5775 	status = set_iqm_af(state, true);  in set_qam_standard()
5776 	if (status < 0)  in set_qam_standard()
5778 	status = write16(state, IQM_AF_START_LOCK__A, 0x01);  in set_qam_standard()
5779 	if (status < 0)  in set_qam_standard()
5783 	status = adc_synchronization(state);  in set_qam_standard()
5784 	if (status < 0)  in set_qam_standard()
5788 	status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);  in set_qam_standard()
5789 	if (status < 0)  in set_qam_standard()
5793 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_qam_standard()
5794 	if (status < 0)  in set_qam_standard()
5800 	status = init_agc(state, true);  in set_qam_standard()
5801 	if (status < 0)  in set_qam_standard()
5803 	status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));  in set_qam_standard()
5804 	if (status < 0)  in set_qam_standard()
5808 	status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);  in set_qam_standard()
5809 	if (status < 0)  in set_qam_standard()
5811 	status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);  in set_qam_standard()
5812 	if (status < 0)  in set_qam_standard()
5816 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_qam_standard()
5818 	if (status < 0)  in set_qam_standard()
5819 		pr_err("Error %d on %s\n", status, __func__);  in set_qam_standard()
5820 	return status;  in set_qam_standard()
5825 	int status;  in write_gpio()  local
5830 	status = write16(state, SCU_RAM_GPIO__A,  in write_gpio()
5832 	if (status < 0)  in write_gpio()
5836 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in write_gpio()
5837 	if (status < 0)  in write_gpio()
5843 			status = write16(state, SIO_PDR_SMA_TX_CFG__A,  in write_gpio()
5845 			if (status < 0)  in write_gpio()
5849 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);  in write_gpio()
5850 			if (status < 0)  in write_gpio()
5857 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);  in write_gpio()
5858 			if (status < 0)  in write_gpio()
5863 			status = write16(state, SIO_PDR_SMA_RX_CFG__A,  in write_gpio()
5865 			if (status < 0)  in write_gpio()
5869 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);  in write_gpio()
5870 			if (status < 0)  in write_gpio()
5877 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);  in write_gpio()
5878 			if (status < 0)  in write_gpio()
5883 			status = write16(state, SIO_PDR_GPIO_CFG__A,  in write_gpio()
5885 			if (status < 0)  in write_gpio()
5889 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);  in write_gpio()
5890 			if (status < 0)  in write_gpio()
5897 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);  in write_gpio()
5898 			if (status < 0)  in write_gpio()
5903 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);  in write_gpio()
5905 	if (status < 0)  in write_gpio()
5906 		pr_err("Error %d on %s\n", status, __func__);  in write_gpio()
5907 	return status;  in write_gpio()
5912 	int status = 0;  in switch_antenna_to_qam()  local
5928 		status = write_gpio(state);  in switch_antenna_to_qam()
5930 	if (status < 0)  in switch_antenna_to_qam()
5931 		pr_err("Error %d on %s\n", status, __func__);  in switch_antenna_to_qam()
5932 	return status;  in switch_antenna_to_qam()
5937 	int status = 0;  in switch_antenna_to_dvbt()  local
5953 		status = write_gpio(state);  in switch_antenna_to_dvbt()
5955 	if (status < 0)  in switch_antenna_to_dvbt()
5956 		pr_err("Error %d on %s\n", status, __func__);  in switch_antenna_to_dvbt()
5957 	return status;  in switch_antenna_to_dvbt()
5969 	int status;  in power_down_device()  local
5974 		status = ConfigureI2CBridge(state, true);  in power_down_device()
5975 		if (status < 0)  in power_down_device()
5979 	status = dvbt_enable_ofdm_token_ring(state, false);  in power_down_device()
5980 	if (status < 0)  in power_down_device()
5983 	status = write16(state, SIO_CC_PWD_MODE__A,  in power_down_device()
5985 	if (status < 0)  in power_down_device()
5987 	status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in power_down_device()
5988 	if (status < 0)  in power_down_device()
5991 	status = hi_cfg_command(state);  in power_down_device()
5993 	if (status < 0)  in power_down_device()
5994 		pr_err("Error %d on %s\n", status, __func__);  in power_down_device()
5996 	return status;  in power_down_device()
6001 	int status = 0, n = 0;  in init_drxk()  local
6008 		status = power_up_device(state);  in init_drxk()
6009 		if (status < 0)  in init_drxk()
6011 		status = drxx_open(state);  in init_drxk()
6012 		if (status < 0)  in init_drxk()
6015 		status = write16(state, SIO_CC_SOFT_RST__A,  in init_drxk()
6019 		if (status < 0)  in init_drxk()
6021 		status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in init_drxk()
6022 		if (status < 0)  in init_drxk()
6030 		status = get_device_capabilities(state);  in init_drxk()
6031 		if (status < 0)  in init_drxk()
6051 		status = init_hi(state);  in init_drxk()
6052 		if (status < 0)  in init_drxk()
6060 			status = write16(state, SCU_RAM_GPIO__A,  in init_drxk()
6062 			if (status < 0)  in init_drxk()
6067 		status = mpegts_disable(state);  in init_drxk()
6068 		if (status < 0)  in init_drxk()
6072 		status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);  in init_drxk()
6073 		if (status < 0)  in init_drxk()
6075 		status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);  in init_drxk()
6076 		if (status < 0)  in init_drxk()
6080 		status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,  in init_drxk()
6082 		if (status < 0)  in init_drxk()
6086 		status = write16(state, SIO_BL_COMM_EXEC__A,  in init_drxk()
6088 		if (status < 0)  in init_drxk()
6090 		status = bl_chain_cmd(state, 0, 6, 100);  in init_drxk()
6091 		if (status < 0)  in init_drxk()
6095 			status = download_microcode(state, state->fw->data,  in init_drxk()
6097 			if (status < 0)  in init_drxk()
6102 		status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,  in init_drxk()
6104 		if (status < 0)  in init_drxk()
6108 		status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in init_drxk()
6109 		if (status < 0)  in init_drxk()
6111 		status = drxx_open(state);  in init_drxk()
6112 		if (status < 0)  in init_drxk()
6118 		status = ctrl_power_mode(state, &power_mode);  in init_drxk()
6119 		if (status < 0)  in init_drxk()
6133 		status = write16(state, SCU_RAM_DRIVER_VER_HI__A,  in init_drxk()
6135 		if (status < 0)  in init_drxk()
6142 		status = write16(state, SCU_RAM_DRIVER_VER_LO__A,  in init_drxk()
6144 		if (status < 0)  in init_drxk()
6162 		status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);  in init_drxk()
6163 		if (status < 0)  in init_drxk()
6168 		status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);  in init_drxk()
6169 		if (status < 0)  in init_drxk()
6172 		status = mpegts_dto_init(state);  in init_drxk()
6173 		if (status < 0)  in init_drxk()
6175 		status = mpegts_stop(state);  in init_drxk()
6176 		if (status < 0)  in init_drxk()
6178 		status = mpegts_configure_polarity(state);  in init_drxk()
6179 		if (status < 0)  in init_drxk()
6181 		status = mpegts_configure_pins(state, state->m_enable_mpeg_output);  in init_drxk()
6182 		if (status < 0)  in init_drxk()
6185 		status = write_gpio(state);  in init_drxk()
6186 		if (status < 0)  in init_drxk()
6192 			status = power_down_device(state);  in init_drxk()
6193 			if (status < 0)  in init_drxk()
6215 	if (status < 0) {  in init_drxk()
6218 		pr_err("Error %d on %s\n", status, __func__);  in init_drxk()
6221 	return status;  in init_drxk()
6364 	int status;  in get_strength()  local
6390 		status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);  in get_strength()
6391 		if (status < 0)  in get_strength()
6392 			return status;  in get_strength()
6395 		status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);  in get_strength()
6396 		if (status < 0)  in get_strength()
6397 			return status;  in get_strength()
6423 		status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,  in get_strength()
6425 		if (status < 0)  in get_strength()
6426 			return status;  in get_strength()
6428 		status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,  in get_strength()
6430 		if (status < 0)  in get_strength()
6431 			return status;  in get_strength()
6467 	int status;  in drxk_get_stats()  local
6530 	status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, &reg16);  in drxk_get_stats()
6531 	if (status < 0)  in drxk_get_stats()
6535 	status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , &reg16);  in drxk_get_stats()
6536 	if (status < 0)  in drxk_get_stats()
6541 	status = read16(state, FEC_RS_NR_BIT_ERRORS__A, &reg16);  in drxk_get_stats()
6542 	if (status < 0)  in drxk_get_stats()
6546 	status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, &reg16);  in drxk_get_stats()
6547 	if (status < 0)  in drxk_get_stats()
6551 	status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, &reg16);  in drxk_get_stats()
6552 	if (status < 0)  in drxk_get_stats()
6556 	status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &reg16);  in drxk_get_stats()
6557 	if (status < 0)  in drxk_get_stats()
6583 	return status;  in drxk_get_stats()
6587 static int drxk_read_status(struct dvb_frontend *fe, enum fe_status *status)  in drxk_read_status()  argument
6598 	*status = state->fe_status;  in drxk_read_status()
6723 	int status;  in drxk_attach()  local
6780 		status = request_firmware(&fw, state->microcode_name,  in drxk_attach()
6782 		if (status < 0)  in drxk_attach()