Lines Matching refs:xSR
114 u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */ member
159 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); in imx_mu_tx_waiting_write()
183 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); in imx_mu_rx_waiting_read()
252 priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_generic_rxdb()
294 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR], in imx_mu_specific_tx()
341 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr, in imx_mu_specific_rx()
458 priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_seco_rxdb()
493 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); in imx_mu_isr()
499 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); in imx_mu_isr()
505 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_isr()
616 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr, in imx_mu_shutdown()
741 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_init_generic()
742 imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_init_generic()
896 .xSR = {0x20, 0x20, 0x20, 0x20},
907 .xSR = {0x60, 0x60, 0x60, 0x60},
919 .xSR = {0xC, 0x118, 0x124, 0x12C},
930 .xSR = {0xC, 0x118, 0x124, 0x12C},
941 .xSR = {0xC, 0x118, 0x124, 0x12C},
952 .xSR = {0x20, 0x20, 0x20, 0x20},
963 .xSR = {0x20, 0x20, 0x20, 0x20},