1 // SPDX-License-Identifier: GPL-2.0-or-later
5  * Based on irq-lpc32xx:
6  *   Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
7  * Based on irq-bcm2836:
14  * - 896 level-triggered hardware IRQs
15  *   - Single mask bit per IRQ
16  *   - Per-IRQ affinity setting
17  *   - Automatic masking on event delivery (auto-ack)
18  *   - Software triggering (ORed with hw line)
19  * - 2 per-CPU IPIs (meant as "self" and "other", but they are
21  * - Automatic prioritization (single event/ack register per CPU, lower IRQs =
23  * - Automatic masking on ack
24  * - Default "this CPU" register view and explicit per-CPU views
32  * - This driver creates two IRQ domains, one for HW IRQs and internal FIQs,
34  * - Since Linux needs more than 2 IPIs, we implement a software IRQ controller
35  *   and funnel all IPIs into one per-CPU IPI (the second "self" IPI is unused).
36  * - FIQ hwirq numbers are assigned after true hwirqs, and are per-cpu.
37  * - DT bindings use 3-cell form (like GIC):
38  *   - <0 nr flags> - hwirq #nr
39  *   - <1 nr flags> - FIQ #nr
40  *     - nr=0  Physical HV timer
41  *     - nr=1  Virtual HV timer
42  *     - nr=2  Physical guest timer
43  *     - nr=3  Virtual guest timer
53 #include <linux/irqchip/arm-vgic-info.h>
65 #include <dt-bindings/interrupt-controller/apple-aic.h>
152  * register as a second reg entry in the device tree to remain
153  * forward-compatible.
163  * IMP-DEF sysregs that control FIQ sources
182 /* Guest timer FIQ enable register */
216  * FIQ hwirq index definitions: FIQ sources use the DT binding defines
225 	/* Must be ordered as in apple-aic.h */
283 		.compatible = "apple,t8103-aic",
321 	return readl_relaxed(ic->base + reg);  in aic_ic_read()
326 	writel_relaxed(val, ic->base + reg);  in aic_ic_write()
338 	u32 off = AIC_HWIRQ_DIE(hwirq) * ic->info.die_stride;  in aic_irq_mask()
341 	aic_ic_write(ic, ic->info.mask_set + off + MASK_REG(irq), MASK_BIT(irq));  in aic_irq_mask()
349 	u32 off = AIC_HWIRQ_DIE(hwirq) * ic->info.die_stride;  in aic_irq_unmask()
352 	aic_ic_write(ic, ic->info.mask_clr + off + MASK_REG(irq), MASK_BIT(irq));  in aic_irq_unmask()
375 		event = readl(ic->event + ic->info.event);  in aic_handle_irq()
380 			generic_handle_domain_irq(aic_irqc->hw_domain, event);  in aic_handle_irq()
395 		generic_handle_domain_irq(aic_irqc->hw_domain,  in aic_handle_irq()
413 	BUG_ON(!ic->info.target_cpu);  in aic_irq_set_affinity()
420 	aic_ic_write(ic, ic->info.target_cpu + AIC_HWIRQ_IRQ(hwirq) * 4, BIT(cpu));  in aic_irq_set_affinity()
432 	return (type == IRQ_TYPE_LEVEL_HIGH || type == IRQ_TYPE_EDGE_RISING) ? 0 : -EINVAL;  in aic_irq_set_type()
453  * FIQ irqchip
522 	 * the FIQ source state without having to peek down into sources...  in aic_handle_fiq()
526 	 *  - Fast IPIs (not yet used)  in aic_handle_fiq()
527 	 *  - The 4 timers (CNTP, CNTV for each of HV and guest)  in aic_handle_fiq()
528 	 *  - Per-core PMCs (not yet supported)  in aic_handle_fiq()
529 	 *  - Per-cluster uncore PMCs (not yet supported)  in aic_handle_fiq()
531 	 * Since not dealing with any of these results in a FIQ storm,  in aic_handle_fiq()
545 		generic_handle_domain_irq(aic_irqc->hw_domain,  in aic_handle_fiq()
549 		generic_handle_domain_irq(aic_irqc->hw_domain,  in aic_handle_fiq()
557 			generic_handle_domain_irq(aic_irqc->hw_domain,  in aic_handle_fiq()
562 			generic_handle_domain_irq(aic_irqc->hw_domain,  in aic_handle_fiq()
569 				     &aic_irqc->fiq_aff[AIC_CPU_PMU_P]->aff))  in aic_handle_fiq()
573 		generic_handle_domain_irq(aic_irqc->hw_domain,  in aic_handle_fiq()
580 		pr_err_ratelimited("Uncore PMC FIQ fired. Masking.\n");  in aic_handle_fiq()
588 	return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL;  in aic_fiq_set_type()
592 	.name = "AIC-FIQ",
607 	struct aic_irq_chip *ic = id->host_data;  in aic_irq_domain_map()
611 	if (ic->info.version == 2)  in aic_irq_domain_map()
615 		irq_domain_set_info(id, irq, hw, chip, id->host_data,  in aic_irq_domain_map()
619 		int fiq = FIELD_GET(AIC_EVENT_NUM, hw);  in aic_irq_domain_map()  local
621 		switch (fiq) {  in aic_irq_domain_map()
624 			irq_set_percpu_devid_partition(irq, &ic->fiq_aff[fiq]->aff);  in aic_irq_domain_map()
631 		irq_domain_set_info(id, irq, hw, &fiq_chip, id->host_data,  in aic_irq_domain_map()
643 	struct aic_irq_chip *ic = id->host_data;  in aic_irq_domain_translate()
647 	if (fwspec->param_count < 3 || fwspec->param_count > 4 ||  in aic_irq_domain_translate()
648 	    !is_of_node(fwspec->fwnode))  in aic_irq_domain_translate()
649 		return -EINVAL;  in aic_irq_domain_translate()
651 	args = &fwspec->param[1];  in aic_irq_domain_translate()
653 	if (fwspec->param_count == 4) {  in aic_irq_domain_translate()
658 	switch (fwspec->param[0]) {  in aic_irq_domain_translate()
660 		if (die >= ic->nr_die)  in aic_irq_domain_translate()
661 			return -EINVAL;  in aic_irq_domain_translate()
662 		if (args[0] >= ic->nr_irq)  in aic_irq_domain_translate()
663 			return -EINVAL;  in aic_irq_domain_translate()
668 			return -EINVAL;  in aic_irq_domain_translate()
670 			return -EINVAL;  in aic_irq_domain_translate()
674 		 * In EL1 the non-redirected registers are the guest's,  in aic_irq_domain_translate()
687 				return -ENOENT;  in aic_irq_domain_translate()
694 		return -EINVAL;  in aic_irq_domain_translate()
802 		return -ENODEV;  in aic_init_smp()
811 	/* Mask all hard-wired per-CPU IRQ/FIQ sources */  in aic_init_cpu()
820 	/* EL2-only (VHE mode) IRQ sources */  in aic_init_cpu()
830 	/* PMC FIQ */  in aic_init_cpu()
834 	/* Uncore PMC FIQ */  in aic_init_cpu()
841 	if (aic_irqc->info.version == 1) {  in aic_init_cpu()
850 		 * Always keep IPIs unmasked at the hardware level (except auto-masking  in aic_init_cpu()
878 	u32 fiq;  in build_fiq_affinity()  local
880 	if (of_property_read_u32(aff, "apple,fiq-index", &fiq) ||  in build_fiq_affinity()
881 	    WARN_ON(fiq >= AIC_NR_FIQ) || ic->fiq_aff[fiq])  in build_fiq_affinity()
888 	ic->fiq_aff[fiq] = kzalloc(sizeof(*ic->fiq_aff[fiq]), GFP_KERNEL);  in build_fiq_affinity()
889 	if (!ic->fiq_aff[fiq])  in build_fiq_affinity()
909 		cpumask_set_cpu(cpu, &ic->fiq_aff[fiq]->aff);  in build_fiq_affinity()
924 		return -EIO;  in aic_of_ic_init()
929 		return -ENOMEM;  in aic_of_ic_init()
932 	irqc->base = regs;  in aic_of_ic_init()
938 	irqc->info = *(struct aic_info *)match->data;  in aic_of_ic_init()
942 	switch (irqc->info.version) {  in aic_of_ic_init()
947 		irqc->nr_irq = FIELD_GET(AIC_INFO_NR_IRQ, info);  in aic_of_ic_init()
948 		irqc->max_irq = AIC_MAX_IRQ;  in aic_of_ic_init()
949 		irqc->nr_die = irqc->max_die = 1;  in aic_of_ic_init()
951 		off = start_off = irqc->info.target_cpu;  in aic_of_ic_init()
952 		off += sizeof(u32) * irqc->max_irq; /* TARGET_CPU */  in aic_of_ic_init()
954 		irqc->event = irqc->base;  in aic_of_ic_init()
964 		irqc->nr_irq = FIELD_GET(AIC2_INFO1_NR_IRQ, info1);  in aic_of_ic_init()
965 		irqc->max_irq = FIELD_GET(AIC2_INFO3_MAX_IRQ, info3);  in aic_of_ic_init()
966 		irqc->nr_die = FIELD_GET(AIC2_INFO1_LAST_DIE, info1) + 1;  in aic_of_ic_init()
967 		irqc->max_die = FIELD_GET(AIC2_INFO3_MAX_DIE, info3);  in aic_of_ic_init()
969 		off = start_off = irqc->info.irq_cfg;  in aic_of_ic_init()
970 		off += sizeof(u32) * irqc->max_irq; /* IRQ_CFG */  in aic_of_ic_init()
972 		irqc->event = of_iomap(node, 1);  in aic_of_ic_init()
973 		if (WARN_ON(!irqc->event))  in aic_of_ic_init()
980 	irqc->info.sw_set = off;  in aic_of_ic_init()
981 	off += sizeof(u32) * (irqc->max_irq >> 5); /* SW_SET */  in aic_of_ic_init()
982 	irqc->info.sw_clr = off;  in aic_of_ic_init()
983 	off += sizeof(u32) * (irqc->max_irq >> 5); /* SW_CLR */  in aic_of_ic_init()
984 	irqc->info.mask_set = off;  in aic_of_ic_init()
985 	off += sizeof(u32) * (irqc->max_irq >> 5); /* MASK_SET */  in aic_of_ic_init()
986 	irqc->info.mask_clr = off;  in aic_of_ic_init()
987 	off += sizeof(u32) * (irqc->max_irq >> 5); /* MASK_CLR */  in aic_of_ic_init()
988 	off += sizeof(u32) * (irqc->max_irq >> 5); /* HW_STATE */  in aic_of_ic_init()
990 	if (irqc->info.fast_ipi)  in aic_of_ic_init()
995 	irqc->info.die_stride = off - start_off;  in aic_of_ic_init()
997 	irqc->hw_domain = irq_domain_create_tree(of_node_to_fwnode(node),  in aic_of_ic_init()
999 	if (WARN_ON(!irqc->hw_domain))  in aic_of_ic_init()
1002 	irq_domain_update_bus_token(irqc->hw_domain, DOMAIN_BUS_WIRED);  in aic_of_ic_init()
1020 	for (die = 0; die < irqc->nr_die; die++) {  in aic_of_ic_init()
1021 		for (i = 0; i < BITS_TO_U32(irqc->nr_irq); i++)  in aic_of_ic_init()
1022 			aic_ic_write(irqc, irqc->info.mask_set + off + i * 4, U32_MAX);  in aic_of_ic_init()
1023 		for (i = 0; i < BITS_TO_U32(irqc->nr_irq); i++)  in aic_of_ic_init()
1024 			aic_ic_write(irqc, irqc->info.sw_clr + off + i * 4, U32_MAX);  in aic_of_ic_init()
1025 		if (irqc->info.target_cpu)  in aic_of_ic_init()
1026 			for (i = 0; i < irqc->nr_irq; i++)  in aic_of_ic_init()
1027 				aic_ic_write(irqc, irqc->info.target_cpu + off + i * 4, 1);  in aic_of_ic_init()
1028 		off += irqc->info.die_stride;  in aic_of_ic_init()
1031 	if (irqc->info.version == 2) {  in aic_of_ic_init()
1045 			  "irqchip/apple-aic/ipi:starting",  in aic_of_ic_init()
1066 		irqc->nr_irq, irqc->max_irq, irqc->nr_die, irqc->max_die, AIC_NR_FIQ, AIC_NR_SWIPI);  in aic_of_ic_init()
1071 	irq_domain_remove(irqc->hw_domain);  in aic_of_ic_init()
1073 	if (irqc->event && irqc->event != irqc->base)  in aic_of_ic_init()
1074 		iounmap(irqc->event);  in aic_of_ic_init()
1075 	iounmap(irqc->base);  in aic_of_ic_init()
1077 	return -ENODEV;  in aic_of_ic_init()