1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
13 #include <linux/io-pgtable.h>
18 #include <linux/iommu.h>
25 #include "msm_iommu_hw-8xxx.h"
54 static int __enable_clocks(struct msm_iommu_dev *iommu)  in __enable_clocks()  argument
58 	ret = clk_enable(iommu->pclk);  in __enable_clocks()
62 	if (iommu->clk) {  in __enable_clocks()
63 		ret = clk_enable(iommu->clk);  in __enable_clocks()
65 			clk_disable(iommu->pclk);  in __enable_clocks()
71 static void __disable_clocks(struct msm_iommu_dev *iommu)  in __disable_clocks()  argument
73 	if (iommu->clk)  in __disable_clocks()
74 		clk_disable(iommu->clk);  in __disable_clocks()
75 	clk_disable(iommu->pclk);  in __disable_clocks()
120 	struct msm_iommu_dev *iommu = NULL;  in __flush_iotlb()  local
124 	list_for_each_entry(iommu, &priv->list_attached, dom_node) {  in __flush_iotlb()
125 		ret = __enable_clocks(iommu);  in __flush_iotlb()
129 		list_for_each_entry(master, &iommu->ctx_list, list)  in __flush_iotlb()
130 			SET_CTX_TLBIALL(iommu->base, master->num, 0);  in __flush_iotlb()
132 		__disable_clocks(iommu);  in __flush_iotlb()
142 	struct msm_iommu_dev *iommu = NULL;  in __flush_iotlb_range()  local
147 	list_for_each_entry(iommu, &priv->list_attached, dom_node) {  in __flush_iotlb_range()
148 		ret = __enable_clocks(iommu);  in __flush_iotlb_range()
152 		list_for_each_entry(master, &iommu->ctx_list, list) {  in __flush_iotlb_range()
156 				iova |= GET_CONTEXTIDR_ASID(iommu->base,  in __flush_iotlb_range()
157 							    master->num);  in __flush_iotlb_range()
158 				SET_TLBIVA(iommu->base, master->num, iova);  in __flush_iotlb_range()
160 			} while (temp_size -= granule);  in __flush_iotlb_range()
163 		__disable_clocks(iommu);  in __flush_iotlb_range()
188 static int msm_iommu_alloc_ctx(unsigned long *map, int start, int end)  in msm_iommu_alloc_ctx()  argument
193 		idx = find_next_zero_bit(map, end, start);  in msm_iommu_alloc_ctx()
195 			return -ENOSPC;  in msm_iommu_alloc_ctx()
196 	} while (test_and_set_bit(idx, map));  in msm_iommu_alloc_ctx()
201 static void msm_iommu_free_ctx(unsigned long *map, int idx)  in msm_iommu_free_ctx()  argument
203 	clear_bit(idx, map);  in msm_iommu_free_ctx()
206 static void config_mids(struct msm_iommu_dev *iommu,  in config_mids()  argument
211 	for (i = 0; i < master->num_mids; i++) {  in config_mids()
212 		mid = master->mids[i];  in config_mids()
213 		ctx = master->num;  in config_mids()
215 		SET_M2VCBR_N(iommu->base, mid, 0);  in config_mids()
216 		SET_CBACR_N(iommu->base, ctx, 0);  in config_mids()
219 		SET_VMID(iommu->base, mid, 0);  in config_mids()
222 		SET_CBNDX(iommu->base, mid, ctx);  in config_mids()
225 		SET_CBVMID(iommu->base, ctx, 0);  in config_mids()
228 		SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx);  in config_mids()
230 		/* Set security bit override to be Non-secure */  in config_mids()
231 		SET_NSCFG(iommu->base, mid, 3);  in config_mids()
273 	SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr);  in __program_context()
274 	SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr);  in __program_context()
278 	SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr);  in __program_context()
279 	SET_NMRR(base, ctx, priv->cfg.arm_v7s_cfg.nmrr);  in __program_context()
316 	INIT_LIST_HEAD(&priv->list_attached);  in msm_iommu_domain_alloc()
318 	priv->domain.geometry.aperture_start = 0;  in msm_iommu_domain_alloc()
319 	priv->domain.geometry.aperture_end   = (1ULL << 32) - 1;  in msm_iommu_domain_alloc()
320 	priv->domain.geometry.force_aperture = true;  in msm_iommu_domain_alloc()
322 	return &priv->domain;  in msm_iommu_domain_alloc()
342 	spin_lock_init(&priv->pgtlock);  in msm_iommu_domain_config()
344 	priv->cfg = (struct io_pgtable_cfg) {  in msm_iommu_domain_config()
349 		.iommu_dev = priv->dev,  in msm_iommu_domain_config()
352 	priv->iop = alloc_io_pgtable_ops(ARM_V7S, &priv->cfg, priv);  in msm_iommu_domain_config()
353 	if (!priv->iop) {  in msm_iommu_domain_config()
354 		dev_err(priv->dev, "Failed to allocate pgtable\n");  in msm_iommu_domain_config()
355 		return -EINVAL;  in msm_iommu_domain_config()
358 	msm_iommu_ops.pgsize_bitmap = priv->cfg.pgsize_bitmap;  in msm_iommu_domain_config()
366 	struct msm_iommu_dev *iommu, *ret = NULL;  in find_iommu_for_dev()  local
369 	list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {  in find_iommu_for_dev()
370 		master = list_first_entry(&iommu->ctx_list,  in find_iommu_for_dev()
373 		if (master->of_node == dev->of_node) {  in find_iommu_for_dev()
374 			ret = iommu;  in find_iommu_for_dev()
384 	struct msm_iommu_dev *iommu;  in msm_iommu_probe_device()  local
388 	iommu = find_iommu_for_dev(dev);  in msm_iommu_probe_device()
391 	if (!iommu)  in msm_iommu_probe_device()
392 		return ERR_PTR(-ENODEV);  in msm_iommu_probe_device()
394 	return &iommu->iommu;  in msm_iommu_probe_device()
401 	struct msm_iommu_dev *iommu;  in msm_iommu_attach_dev()  local
405 	priv->dev = dev;  in msm_iommu_attach_dev()
409 	list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {  in msm_iommu_attach_dev()
410 		master = list_first_entry(&iommu->ctx_list,  in msm_iommu_attach_dev()
413 		if (master->of_node == dev->of_node) {  in msm_iommu_attach_dev()
414 			ret = __enable_clocks(iommu);  in msm_iommu_attach_dev()
418 			list_for_each_entry(master, &iommu->ctx_list, list) {  in msm_iommu_attach_dev()
419 				if (master->num) {  in msm_iommu_attach_dev()
421 					ret = -EEXIST;  in msm_iommu_attach_dev()
424 				master->num =  in msm_iommu_attach_dev()
425 					msm_iommu_alloc_ctx(iommu->context_map,  in msm_iommu_attach_dev()
426 							    0, iommu->ncb);  in msm_iommu_attach_dev()
427 				if (IS_ERR_VALUE(master->num)) {  in msm_iommu_attach_dev()
428 					ret = -ENODEV;  in msm_iommu_attach_dev()
431 				config_mids(iommu, master);  in msm_iommu_attach_dev()
432 				__program_context(iommu->base, master->num,  in msm_iommu_attach_dev()
435 			__disable_clocks(iommu);  in msm_iommu_attach_dev()
436 			list_add(&iommu->dom_node, &priv->list_attached);  in msm_iommu_attach_dev()
451 	struct msm_iommu_dev *iommu;  in msm_iommu_set_platform_dma()  local
455 	free_io_pgtable_ops(priv->iop);  in msm_iommu_set_platform_dma()
458 	list_for_each_entry(iommu, &priv->list_attached, dom_node) {  in msm_iommu_set_platform_dma()
459 		ret = __enable_clocks(iommu);  in msm_iommu_set_platform_dma()
463 		list_for_each_entry(master, &iommu->ctx_list, list) {  in msm_iommu_set_platform_dma()
464 			msm_iommu_free_ctx(iommu->context_map, master->num);  in msm_iommu_set_platform_dma()
465 			__reset_context(iommu->base, master->num);  in msm_iommu_set_platform_dma()
467 		__disable_clocks(iommu);  in msm_iommu_set_platform_dma()
481 	spin_lock_irqsave(&priv->pgtlock, flags);  in msm_iommu_map()
482 	ret = priv->iop->map_pages(priv->iop, iova, pa, pgsize, pgcount, prot,  in msm_iommu_map()
484 	spin_unlock_irqrestore(&priv->pgtlock, flags);  in msm_iommu_map()
505 	spin_lock_irqsave(&priv->pgtlock, flags);  in msm_iommu_unmap()
506 	ret = priv->iop->unmap_pages(priv->iop, iova, pgsize, pgcount, gather);  in msm_iommu_unmap()
507 	spin_unlock_irqrestore(&priv->pgtlock, flags);  in msm_iommu_unmap()
516 	struct msm_iommu_dev *iommu;  in msm_iommu_iova_to_phys()  local
525 	iommu = list_first_entry(&priv->list_attached,  in msm_iommu_iova_to_phys()
528 	if (list_empty(&iommu->ctx_list))  in msm_iommu_iova_to_phys()
531 	master = list_first_entry(&iommu->ctx_list,  in msm_iommu_iova_to_phys()
536 	ret = __enable_clocks(iommu);  in msm_iommu_iova_to_phys()
541 	SET_CTX_TLBIALL(iommu->base, master->num, 0);  in msm_iommu_iova_to_phys()
542 	SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA);  in msm_iommu_iova_to_phys()
544 	par = GET_PAR(iommu->base, master->num);  in msm_iommu_iova_to_phys()
547 	if (GET_NOFAULT_SS(iommu->base, master->num))  in msm_iommu_iova_to_phys()
552 	if (GET_FAULT(iommu->base, master->num))  in msm_iommu_iova_to_phys()
555 	__disable_clocks(iommu);  in msm_iommu_iova_to_phys()
587 				struct msm_iommu_dev **iommu,  in insert_iommu_master()  argument
593 	if (list_empty(&(*iommu)->ctx_list)) {  in insert_iommu_master()
597 			return -ENOMEM;  in insert_iommu_master()
599 		master->of_node = dev->of_node;  in insert_iommu_master()
600 		list_add(&master->list, &(*iommu)->ctx_list);  in insert_iommu_master()
604 	for (sid = 0; sid < master->num_mids; sid++)  in insert_iommu_master()
605 		if (master->mids[sid] == spec->args[0]) {  in insert_iommu_master()
611 	master->mids[master->num_mids++] = spec->args[0];  in insert_iommu_master()
618 	struct msm_iommu_dev *iommu = NULL, *iter;  in qcom_iommu_of_xlate()  local
624 		if (iter->dev->of_node == spec->np) {  in qcom_iommu_of_xlate()
625 			iommu = iter;  in qcom_iommu_of_xlate()
630 	if (!iommu) {  in qcom_iommu_of_xlate()
631 		ret = -ENODEV;  in qcom_iommu_of_xlate()
635 	ret = insert_iommu_master(dev, &iommu, spec);  in qcom_iommu_of_xlate()
644 	struct msm_iommu_dev *iommu = dev_id;  in msm_iommu_fault_handler()  local
650 	if (!iommu) {  in msm_iommu_fault_handler()
655 	pr_err("Unexpected IOMMU page fault!\n");  in msm_iommu_fault_handler()
656 	pr_err("base = %08x\n", (unsigned int)iommu->base);  in msm_iommu_fault_handler()
658 	ret = __enable_clocks(iommu);  in msm_iommu_fault_handler()
662 	for (i = 0; i < iommu->ncb; i++) {  in msm_iommu_fault_handler()
663 		fsr = GET_FSR(iommu->base, i);  in msm_iommu_fault_handler()
667 			print_ctx_regs(iommu->base, i);  in msm_iommu_fault_handler()
668 			SET_FSR(iommu->base, i, 0x4000000F);  in msm_iommu_fault_handler()
671 	__disable_clocks(iommu);  in msm_iommu_fault_handler()
691 		 * taken care when the iommu client does a writel before
705 	struct msm_iommu_dev *iommu;  in msm_iommu_probe()  local
708 	iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL);  in msm_iommu_probe()
709 	if (!iommu)  in msm_iommu_probe()
710 		return -ENODEV;  in msm_iommu_probe()
712 	iommu->dev = &pdev->dev;  in msm_iommu_probe()
713 	INIT_LIST_HEAD(&iommu->ctx_list);  in msm_iommu_probe()
715 	iommu->pclk = devm_clk_get(iommu->dev, "smmu_pclk");  in msm_iommu_probe()
716 	if (IS_ERR(iommu->pclk))  in msm_iommu_probe()
717 		return dev_err_probe(iommu->dev, PTR_ERR(iommu->pclk),  in msm_iommu_probe()
720 	ret = clk_prepare(iommu->pclk);  in msm_iommu_probe()
722 		return dev_err_probe(iommu->dev, ret,  in msm_iommu_probe()
725 	iommu->clk = devm_clk_get(iommu->dev, "iommu_clk");  in msm_iommu_probe()
726 	if (IS_ERR(iommu->clk)) {  in msm_iommu_probe()
727 		clk_unprepare(iommu->pclk);  in msm_iommu_probe()
728 		return dev_err_probe(iommu->dev, PTR_ERR(iommu->clk),  in msm_iommu_probe()
732 	ret = clk_prepare(iommu->clk);  in msm_iommu_probe()
734 		clk_unprepare(iommu->pclk);  in msm_iommu_probe()
735 		return dev_err_probe(iommu->dev, ret, "could not prepare iommu_clk\n");  in msm_iommu_probe()
739 	iommu->base = devm_ioremap_resource(iommu->dev, r);  in msm_iommu_probe()
740 	if (IS_ERR(iommu->base)) {  in msm_iommu_probe()
741 		ret = dev_err_probe(iommu->dev, PTR_ERR(iommu->base), "could not get iommu base\n");  in msm_iommu_probe()
744 	ioaddr = r->start;  in msm_iommu_probe()
746 	iommu->irq = platform_get_irq(pdev, 0);  in msm_iommu_probe()
747 	if (iommu->irq < 0) {  in msm_iommu_probe()
748 		ret = -ENODEV;  in msm_iommu_probe()
752 	ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val);  in msm_iommu_probe()
754 		dev_err(iommu->dev, "could not get ncb\n");  in msm_iommu_probe()
757 	iommu->ncb = val;  in msm_iommu_probe()
759 	msm_iommu_reset(iommu->base, iommu->ncb);  in msm_iommu_probe()
760 	SET_M(iommu->base, 0, 1);  in msm_iommu_probe()
761 	SET_PAR(iommu->base, 0, 0);  in msm_iommu_probe()
762 	SET_V2PCFG(iommu->base, 0, 1);  in msm_iommu_probe()
763 	SET_V2PPR(iommu->base, 0, 0);  in msm_iommu_probe()
764 	par = GET_PAR(iommu->base, 0);  in msm_iommu_probe()
765 	SET_V2PCFG(iommu->base, 0, 0);  in msm_iommu_probe()
766 	SET_M(iommu->base, 0, 0);  in msm_iommu_probe()
770 		ret = -ENODEV;  in msm_iommu_probe()
774 	ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL,  in msm_iommu_probe()
778 					iommu);  in msm_iommu_probe()
780 		pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret);  in msm_iommu_probe()
784 	list_add(&iommu->dev_node, &qcom_iommu_devices);  in msm_iommu_probe()
786 	ret = iommu_device_sysfs_add(&iommu->iommu, iommu->dev, NULL,  in msm_iommu_probe()
787 				     "msm-smmu.%pa", &ioaddr);  in msm_iommu_probe()
789 		pr_err("Could not add msm-smmu at %pa to sysfs\n", &ioaddr);  in msm_iommu_probe()
793 	ret = iommu_device_register(&iommu->iommu, &msm_iommu_ops, &pdev->dev);  in msm_iommu_probe()
795 		pr_err("Could not register msm-smmu at %pa\n", &ioaddr);  in msm_iommu_probe()
800 		iommu->base, iommu->irq, iommu->ncb);  in msm_iommu_probe()
804 	clk_unprepare(iommu->clk);  in msm_iommu_probe()
805 	clk_unprepare(iommu->pclk);  in msm_iommu_probe()
810 	{ .compatible = "qcom,apq8064-iommu" },
816 	struct msm_iommu_dev *iommu = platform_get_drvdata(pdev);  in msm_iommu_remove()  local
818 	clk_unprepare(iommu->clk);  in msm_iommu_remove()
819 	clk_unprepare(iommu->pclk);  in msm_iommu_remove()