Lines Matching +full:pci +full:- +full:rcar +full:- +full:gen2
1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for Renesas VMSA-compatible IPMMU
6 * Copyright (C) 2014-2020 Renesas Electronics Corporation
11 #include <linux/dma-mapping.h>
18 #include <linux/io-pgtable.h>
22 #include <linux/pci.h>
29 #include <asm/dma-iommu.h>
32 #define arm_iommu_attach_device(...) -ENODEV
37 #define IPMMU_CTX_INVALID -1
94 /* -----------------------------------------------------------------------------
101 #define IMCTR 0x0000 /* R-Car Gen2/3 */
102 #define IMCTR_INTEN (1 << 2) /* R-Car Gen2/3 */
103 #define IMCTR_FLUSH (1 << 1) /* R-Car Gen2/3 */
104 #define IMCTR_MMUEN (1 << 0) /* R-Car Gen2/3 */
106 #define IMTTBCR 0x0008 /* R-Car Gen2/3 */
107 #define IMTTBCR_EAE (1 << 31) /* R-Car Gen2/3 */
108 #define IMTTBCR_SH0_INNER_SHAREABLE (3 << 12) /* R-Car Gen2 only */
109 #define IMTTBCR_ORGN0_WB_WA (1 << 10) /* R-Car Gen2 only */
110 #define IMTTBCR_IRGN0_WB_WA (1 << 8) /* R-Car Gen2 only */
111 #define IMTTBCR_SL0_TWOBIT_LVL_1 (2 << 6) /* R-Car Gen3 only */
112 #define IMTTBCR_SL0_LVL_1 (1 << 4) /* R-Car Gen2 only */
114 #define IMBUSCR 0x000c /* R-Car Gen2 only */
115 #define IMBUSCR_DVM (1 << 2) /* R-Car Gen2 only */
116 #define IMBUSCR_BUSSEL_MASK (3 << 0) /* R-Car Gen2 only */
118 #define IMTTLBR0 0x0010 /* R-Car Gen2/3 */
119 #define IMTTUBR0 0x0014 /* R-Car Gen2/3 */
121 #define IMSTR 0x0020 /* R-Car Gen2/3 */
122 #define IMSTR_MHIT (1 << 4) /* R-Car Gen2/3 */
123 #define IMSTR_ABORT (1 << 2) /* R-Car Gen2/3 */
124 #define IMSTR_PF (1 << 1) /* R-Car Gen2/3 */
125 #define IMSTR_TF (1 << 0) /* R-Car Gen2/3 */
127 #define IMMAIR0 0x0028 /* R-Car Gen2/3 */
129 #define IMELAR 0x0030 /* R-Car Gen2/3, IMEAR on R-Car Gen2 */
130 #define IMEUAR 0x0034 /* R-Car Gen3 only */
134 #define IMUCTR0(n) (0x0300 + ((n) * 16)) /* R-Car Gen2/3 */
135 #define IMUCTR32(n) (0x0600 + (((n) - 32) * 16)) /* R-Car Gen3 only */
136 #define IMUCTR_TTSEL_MMU(n) ((n) << 4) /* R-Car Gen2/3 */
137 #define IMUCTR_FLUSH (1 << 1) /* R-Car Gen2/3 */
138 #define IMUCTR_MMUEN (1 << 0) /* R-Car Gen2/3 */
141 #define IMUASID0(n) (0x0308 + ((n) * 16)) /* R-Car Gen2/3 */
142 #define IMUASID32(n) (0x0608 + (((n) - 32) * 16)) /* R-Car Gen3 only */
144 /* -----------------------------------------------------------------------------
152 return mmu->root == mmu; in ipmmu_is_root()
174 /* -----------------------------------------------------------------------------
180 return ioread32(mmu->base + offset); in ipmmu_read()
186 iowrite32(data, mmu->base + offset); in ipmmu_write()
192 unsigned int base = mmu->features->ctx_offset_base; in ipmmu_ctx_reg()
195 base += 0x800 - 8 * 0x40; in ipmmu_ctx_reg()
197 return base + context_id * mmu->features->ctx_offset_stride + reg; in ipmmu_ctx_reg()
215 return ipmmu_ctx_read(domain->mmu->root, domain->context_id, reg); in ipmmu_ctx_read_root()
221 ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data); in ipmmu_ctx_write_root()
227 if (domain->mmu != domain->mmu->root) in ipmmu_ctx_write_all()
228 ipmmu_ctx_write(domain->mmu, domain->context_id, reg, data); in ipmmu_ctx_write_all()
230 ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data); in ipmmu_ctx_write_all()
235 return mmu->features->utlb_offset_base + reg; in ipmmu_utlb_reg()
250 /* -----------------------------------------------------------------------------
262 dev_err_ratelimited(domain->mmu->dev, in ipmmu_tlb_sync()
263 "TLB sync timed out -- MMU may be deadlocked\n"); in ipmmu_tlb_sync()
283 struct ipmmu_vmsa_device *mmu = domain->mmu; in ipmmu_utlb_enable()
286 * TODO: Reference-count the microTLB as several bus masters can be in ipmmu_utlb_enable()
293 ipmmu_imuctr_write(mmu, utlb, IMUCTR_TTSEL_MMU(domain->context_id) | in ipmmu_utlb_enable()
295 mmu->utlb_ctx[utlb] = domain->context_id; in ipmmu_utlb_enable()
316 /* -----------------------------------------------------------------------------
326 spin_lock_irqsave(&mmu->lock, flags); in ipmmu_domain_allocate_context()
328 ret = find_first_zero_bit(mmu->ctx, mmu->num_ctx); in ipmmu_domain_allocate_context()
329 if (ret != mmu->num_ctx) { in ipmmu_domain_allocate_context()
330 mmu->domains[ret] = domain; in ipmmu_domain_allocate_context()
331 set_bit(ret, mmu->ctx); in ipmmu_domain_allocate_context()
333 ret = -EBUSY; in ipmmu_domain_allocate_context()
335 spin_unlock_irqrestore(&mmu->lock, flags); in ipmmu_domain_allocate_context()
345 spin_lock_irqsave(&mmu->lock, flags); in ipmmu_domain_free_context()
347 clear_bit(context_id, mmu->ctx); in ipmmu_domain_free_context()
348 mmu->domains[context_id] = NULL; in ipmmu_domain_free_context()
350 spin_unlock_irqrestore(&mmu->lock, flags); in ipmmu_domain_free_context()
359 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr; in ipmmu_domain_setup_context()
365 * We use long descriptors and allocate the whole 32-bit VA space to in ipmmu_domain_setup_context()
368 if (domain->mmu->features->twobit_imttbcr_sl0) in ipmmu_domain_setup_context()
373 if (domain->mmu->features->cache_snoop) in ipmmu_domain_setup_context()
381 domain->cfg.arm_lpae_s1_cfg.mair); in ipmmu_domain_setup_context()
384 if (domain->mmu->features->setup_imbuscr) in ipmmu_domain_setup_context()
397 * Enable the MMU and interrupt generation. The long-descriptor in ipmmu_domain_setup_context()
413 * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory in ipmmu_domain_init_context()
414 * access, Long-descriptor format" that the NStable bit being set in a in ipmmu_domain_init_context()
419 * non-secure mode. in ipmmu_domain_init_context()
421 domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS; in ipmmu_domain_init_context()
422 domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K; in ipmmu_domain_init_context()
423 domain->cfg.ias = 32; in ipmmu_domain_init_context()
424 domain->cfg.oas = 40; in ipmmu_domain_init_context()
425 domain->cfg.tlb = &ipmmu_flush_ops; in ipmmu_domain_init_context()
426 domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32); in ipmmu_domain_init_context()
427 domain->io_domain.geometry.force_aperture = true; in ipmmu_domain_init_context()
430 * cache handling. For now, delegate it to the io-pgtable code. in ipmmu_domain_init_context()
432 domain->cfg.coherent_walk = false; in ipmmu_domain_init_context()
433 domain->cfg.iommu_dev = domain->mmu->root->dev; in ipmmu_domain_init_context()
438 ret = ipmmu_domain_allocate_context(domain->mmu->root, domain); in ipmmu_domain_init_context()
442 domain->context_id = ret; in ipmmu_domain_init_context()
444 domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg, in ipmmu_domain_init_context()
446 if (!domain->iop) { in ipmmu_domain_init_context()
447 ipmmu_domain_free_context(domain->mmu->root, in ipmmu_domain_init_context()
448 domain->context_id); in ipmmu_domain_init_context()
449 return -EINVAL; in ipmmu_domain_init_context()
458 if (!domain->mmu) in ipmmu_domain_destroy_context()
469 ipmmu_domain_free_context(domain->mmu->root, domain->context_id); in ipmmu_domain_destroy_context()
472 /* -----------------------------------------------------------------------------
479 struct ipmmu_vmsa_device *mmu = domain->mmu; in ipmmu_domain_irq()
501 dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%lx\n", in ipmmu_domain_irq()
504 dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%lx\n", in ipmmu_domain_irq()
516 if (!report_iommu_fault(&domain->io_domain, mmu->dev, iova, 0)) in ipmmu_domain_irq()
519 dev_err_ratelimited(mmu->dev, in ipmmu_domain_irq()
533 spin_lock_irqsave(&mmu->lock, flags); in ipmmu_irq()
538 for (i = 0; i < mmu->num_ctx; i++) { in ipmmu_irq()
539 if (!mmu->domains[i]) in ipmmu_irq()
541 if (ipmmu_domain_irq(mmu->domains[i]) == IRQ_HANDLED) in ipmmu_irq()
545 spin_unlock_irqrestore(&mmu->lock, flags); in ipmmu_irq()
550 /* -----------------------------------------------------------------------------
565 mutex_init(&domain->mutex); in ipmmu_domain_alloc()
567 return &domain->io_domain; in ipmmu_domain_alloc()
579 free_io_pgtable_ops(domain->iop); in ipmmu_domain_free()
594 return -ENXIO; in ipmmu_attach_device()
597 mutex_lock(&domain->mutex); in ipmmu_attach_device()
599 if (!domain->mmu) { in ipmmu_attach_device()
601 domain->mmu = mmu; in ipmmu_attach_device()
605 domain->mmu = NULL; in ipmmu_attach_device()
608 domain->context_id); in ipmmu_attach_device()
610 } else if (domain->mmu != mmu) { in ipmmu_attach_device()
615 ret = -EINVAL; in ipmmu_attach_device()
617 dev_info(dev, "Reusing IPMMU context %u\n", domain->context_id); in ipmmu_attach_device()
619 mutex_unlock(&domain->mutex); in ipmmu_attach_device()
624 for (i = 0; i < fwspec->num_ids; ++i) in ipmmu_attach_device()
625 ipmmu_utlb_enable(domain, fwspec->ids[i]); in ipmmu_attach_device()
636 return domain->iop->map_pages(domain->iop, iova, paddr, pgsize, pgcount, in ipmmu_map()
646 return domain->iop->unmap_pages(domain->iop, iova, pgsize, pgcount, gather); in ipmmu_unmap()
653 if (domain->mmu) in ipmmu_flush_iotlb_all()
670 return domain->iop->iova_to_phys(domain->iop, iova); in ipmmu_iova_to_phys()
678 ipmmu_pdev = of_find_device_by_node(args->np); in ipmmu_init_platform_device()
680 return -ENODEV; in ipmmu_init_platform_device()
688 { .family = "R-Car Gen3", },
689 { .family = "R-Car Gen4", },
713 * R-Car Gen3/4 and RZ/G2 use the allow list to opt-in devices. in ipmmu_device_is_allowed()
723 /* Check whether this device is a PCI device */ in ipmmu_device_is_allowed()
741 return -ENODEV; in ipmmu_of_xlate()
743 iommu_fwspec_add_ids(dev, spec->args, 1); in ipmmu_of_xlate()
745 /* Initialize once - xlate() will call multiple times */ in ipmmu_of_xlate()
762 * - Create one mapping per context (TLB). in ipmmu_init_arm_mapping()
763 * - Make the mapping size configurable ? We currently use a 2GB mapping in ipmmu_init_arm_mapping()
766 if (!mmu->mapping) { in ipmmu_init_arm_mapping()
772 dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n"); in ipmmu_init_arm_mapping()
777 mmu->mapping = mapping; in ipmmu_init_arm_mapping()
781 ret = arm_iommu_attach_device(dev, mmu->mapping); in ipmmu_init_arm_mapping()
790 if (mmu->mapping) in ipmmu_init_arm_mapping()
791 arm_iommu_release_mapping(mmu->mapping); in ipmmu_init_arm_mapping()
804 return ERR_PTR(-ENODEV); in ipmmu_probe_device()
806 return &mmu->iommu; in ipmmu_probe_device()
817 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n"); in ipmmu_probe_finalize()
826 for (i = 0; i < fwspec->num_ids; ++i) { in ipmmu_release_device()
827 unsigned int utlb = fwspec->ids[i]; in ipmmu_release_device()
830 mmu->utlb_ctx[utlb] = IPMMU_CTX_INVALID; in ipmmu_release_device()
833 arm_iommu_release_mapping(mmu->mapping); in ipmmu_release_device()
841 if (mmu->group) in ipmmu_find_group()
842 return iommu_group_ref_get(mmu->group); in ipmmu_find_group()
846 mmu->group = group; in ipmmu_find_group()
871 /* -----------------------------------------------------------------------------
880 for (i = 0; i < mmu->num_ctx; ++i) in ipmmu_device_reset()
928 .compatible = "renesas,ipmmu-vmsa",
931 .compatible = "renesas,ipmmu-r8a774a1",
934 .compatible = "renesas,ipmmu-r8a774b1",
937 .compatible = "renesas,ipmmu-r8a774c0",
940 .compatible = "renesas,ipmmu-r8a774e1",
943 .compatible = "renesas,ipmmu-r8a7795",
946 .compatible = "renesas,ipmmu-r8a7796",
949 .compatible = "renesas,ipmmu-r8a77961",
952 .compatible = "renesas,ipmmu-r8a77965",
955 .compatible = "renesas,ipmmu-r8a77970",
958 .compatible = "renesas,ipmmu-r8a77980",
961 .compatible = "renesas,ipmmu-r8a77990",
964 .compatible = "renesas,ipmmu-r8a77995",
967 .compatible = "renesas,ipmmu-r8a779a0",
970 .compatible = "renesas,rcar-gen4-ipmmu-vmsa",
984 mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL); in ipmmu_probe()
986 dev_err(&pdev->dev, "cannot allocate device data\n"); in ipmmu_probe()
987 return -ENOMEM; in ipmmu_probe()
990 mmu->dev = &pdev->dev; in ipmmu_probe()
991 spin_lock_init(&mmu->lock); in ipmmu_probe()
992 bitmap_zero(mmu->ctx, IPMMU_CTX_MAX); in ipmmu_probe()
993 mmu->features = of_device_get_match_data(&pdev->dev); in ipmmu_probe()
994 memset(mmu->utlb_ctx, IPMMU_CTX_INVALID, mmu->features->num_utlbs); in ipmmu_probe()
995 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); in ipmmu_probe()
1001 mmu->base = devm_ioremap_resource(&pdev->dev, res); in ipmmu_probe()
1002 if (IS_ERR(mmu->base)) in ipmmu_probe()
1003 return PTR_ERR(mmu->base); in ipmmu_probe()
1006 * The IPMMU has two register banks, for secure and non-secure modes. in ipmmu_probe()
1009 * mode the non-secure register bank is also available at an offset. in ipmmu_probe()
1013 * non-secure operation with the main register bank were not successful. in ipmmu_probe()
1014 * Offset the registers base unconditionally to point to the non-secure in ipmmu_probe()
1017 if (mmu->features->use_ns_alias_offset) in ipmmu_probe()
1018 mmu->base += IM_NS_ALIAS_OFFSET; in ipmmu_probe()
1020 mmu->num_ctx = min(IPMMU_CTX_MAX, mmu->features->number_of_contexts); in ipmmu_probe()
1024 * the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property. in ipmmu_probe()
1026 if (!mmu->features->has_cache_leaf_nodes || in ipmmu_probe()
1027 !of_property_present(pdev->dev.of_node, "renesas,ipmmu-main")) in ipmmu_probe()
1028 mmu->root = mmu; in ipmmu_probe()
1030 mmu->root = ipmmu_find_root(); in ipmmu_probe()
1035 if (!mmu->root) in ipmmu_probe()
1036 return -EPROBE_DEFER; in ipmmu_probe()
1044 ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0, in ipmmu_probe()
1045 dev_name(&pdev->dev), mmu); in ipmmu_probe()
1047 dev_err(&pdev->dev, "failed to request IRQ %d\n", irq); in ipmmu_probe()
1053 if (mmu->features->reserved_context) { in ipmmu_probe()
1054 dev_info(&pdev->dev, "IPMMU context 0 is reserved\n"); in ipmmu_probe()
1055 set_bit(0, mmu->ctx); in ipmmu_probe()
1061 * - R-Car Gen2 IPMMU (all devices registered) in ipmmu_probe()
1062 * - R-Car Gen3 IPMMU (leaf devices only - skip root IPMMU-MM device) in ipmmu_probe()
1064 if (!mmu->features->has_cache_leaf_nodes || !ipmmu_is_root(mmu)) { in ipmmu_probe()
1065 ret = iommu_device_sysfs_add(&mmu->iommu, &pdev->dev, NULL, in ipmmu_probe()
1066 dev_name(&pdev->dev)); in ipmmu_probe()
1070 ret = iommu_device_register(&mmu->iommu, &ipmmu_ops, &pdev->dev); in ipmmu_probe()
1090 iommu_device_sysfs_remove(&mmu->iommu); in ipmmu_remove()
1091 iommu_device_unregister(&mmu->iommu); in ipmmu_remove()
1093 arm_iommu_release_mapping(mmu->mapping); in ipmmu_remove()
1108 for (i = 0; i < mmu->num_ctx; i++) { in ipmmu_resume_noirq()
1109 if (!mmu->domains[i]) in ipmmu_resume_noirq()
1112 ipmmu_domain_setup_context(mmu->domains[i]); in ipmmu_resume_noirq()
1116 /* Re-enable active micro-TLBs */ in ipmmu_resume_noirq()
1117 for (i = 0; i < mmu->features->num_utlbs; i++) { in ipmmu_resume_noirq()
1118 if (mmu->utlb_ctx[i] == IPMMU_CTX_INVALID) in ipmmu_resume_noirq()
1121 ipmmu_utlb_enable(mmu->root->domains[mmu->utlb_ctx[i]], i); in ipmmu_resume_noirq()
1137 .name = "ipmmu-vmsa",