Lines Matching defs:intel_iommu

650 struct intel_iommu {  struct
651 	void __iomem	*reg; /* Pointer to hardware regs, virtual addr */
652 	u64 		reg_phys; /* physical address of hw register set */
653 	u64		reg_size; /* size of hw register set */
654 	u64		cap;
655 	u64		ecap;
656 	u64		vccap;
657 	u64		ecmdcap[DMA_MAX_NUM_ECMDCAP];
658 	u32		gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
659 	raw_spinlock_t	register_lock; /* protect register handling */
660 	int		seq_id;	/* sequence id of the iommu */
661 	int		agaw; /* agaw of this iommu */
662 	int		msagaw; /* max sagaw of this iommu */
663 	unsigned int	irq, pr_irq, perf_irq;
664 	u16		segment;     /* PCI segment# */
665 	unsigned char 	name[13];    /* Device Name */
668 	unsigned long 	*domain_ids; /* bitmap of domains */
669 	unsigned long	*copied_tables; /* bitmap of copied tables */
670 	spinlock_t	lock; /* protect context, domain ids */
671 	struct root_entry *root_entry; /* virtual address */
673 	struct iommu_flush flush;
676 	struct page_req_dsc *prq;
677 	unsigned char prq_name[16];    /* Name for PRQ interrupt */
678 	unsigned long prq_seq_number;
679 	struct completion prq_complete;
681 	struct iopf_queue *iopf_queue;
682 	unsigned char iopfq_name[16];
683 	struct q_inval  *qi;            /* Queued invalidation info */
684 	u32 iommu_state[MAX_SR_DMAR_REGS]; /* Store iommu states between suspend and resume.*/
687 	struct ir_table *ir_table;	/* Interrupt remapping info */
688 	struct irq_domain *ir_domain;
690 	struct iommu_device iommu;  /* IOMMU core code handle */
691 	int		node;
692 	u32		flags;      /* Software defined flags */
716 	struct intel_iommu *iommu; /* IOMMU used by this device */  argument