Lines Matching +full:msm8996 +full:- +full:smmu +full:- +full:v2
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
12 #include "arm-smmu.h"
13 #include "arm-smmu-qcom.h"
15 #define QCOM_DUMMY_VAL -1
17 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) in to_qcom_smmu() argument
19 return container_of(smmu, struct qcom_smmu, smmu); in to_qcom_smmu()
22 static void qcom_smmu_tlb_sync(struct arm_smmu_device *smmu, int page, in qcom_smmu_tlb_sync() argument
28 arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL); in qcom_smmu_tlb_sync()
30 for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { in qcom_smmu_tlb_sync()
31 reg = arm_smmu_readl(smmu, page, status); in qcom_smmu_tlb_sync()
39 qcom_smmu_tlb_sync_debug(smmu); in qcom_smmu_tlb_sync()
42 static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, in qcom_adreno_smmu_write_sctlr() argument
45 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); in qcom_adreno_smmu_write_sctlr()
53 if (qsmmu->stall_enabled & BIT(idx)) in qcom_adreno_smmu_write_sctlr()
56 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); in qcom_adreno_smmu_write_sctlr()
63 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in qcom_adreno_smmu_get_fault_info()
64 struct arm_smmu_device *smmu = smmu_domain->smmu; in qcom_adreno_smmu_get_fault_info() local
66 info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR); in qcom_adreno_smmu_get_fault_info()
67 info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0); in qcom_adreno_smmu_get_fault_info()
68 info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1); in qcom_adreno_smmu_get_fault_info()
69 info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR); in qcom_adreno_smmu_get_fault_info()
70 info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx)); in qcom_adreno_smmu_get_fault_info()
71 info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0); in qcom_adreno_smmu_get_fault_info()
72 info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR); in qcom_adreno_smmu_get_fault_info()
78 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in qcom_adreno_smmu_set_stall()
79 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu); in qcom_adreno_smmu_set_stall()
82 qsmmu->stall_enabled |= BIT(cfg->cbndx); in qcom_adreno_smmu_set_stall()
84 qsmmu->stall_enabled &= ~BIT(cfg->cbndx); in qcom_adreno_smmu_set_stall()
90 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in qcom_adreno_smmu_resume_translation()
91 struct arm_smmu_device *smmu = smmu_domain->smmu; in qcom_adreno_smmu_resume_translation() local
97 arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg); in qcom_adreno_smmu_resume_translation()
109 * identify it and configure it for per-instance pagetables in qcom_adreno_smmu_is_gpu_device()
111 for (i = 0; i < fwspec->num_ids; i++) { in qcom_adreno_smmu_is_gpu_device()
112 u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); in qcom_adreno_smmu_is_gpu_device()
126 io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); in qcom_adreno_smmu_get_ttbr1_cfg()
127 return &pgtable->cfg; in qcom_adreno_smmu_get_ttbr1_cfg()
132 * The GPU driver will call this to enable TTBR0 when per-instance pagetables
140 struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); in qcom_adreno_smmu_set_ttbr0_cfg()
141 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in qcom_adreno_smmu_set_ttbr0_cfg()
142 struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; in qcom_adreno_smmu_set_ttbr0_cfg()
145 if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) in qcom_adreno_smmu_set_ttbr0_cfg()
146 return -EINVAL; in qcom_adreno_smmu_set_ttbr0_cfg()
151 if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0)) in qcom_adreno_smmu_set_ttbr0_cfg()
152 return -EINVAL; in qcom_adreno_smmu_set_ttbr0_cfg()
155 cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg); in qcom_adreno_smmu_set_ttbr0_cfg()
156 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); in qcom_adreno_smmu_set_ttbr0_cfg()
158 u32 tcr = cb->tcr[0]; in qcom_adreno_smmu_set_ttbr0_cfg()
161 if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0)) in qcom_adreno_smmu_set_ttbr0_cfg()
162 return -EINVAL; in qcom_adreno_smmu_set_ttbr0_cfg()
167 cb->tcr[0] = tcr; in qcom_adreno_smmu_set_ttbr0_cfg()
168 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in qcom_adreno_smmu_set_ttbr0_cfg()
169 cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); in qcom_adreno_smmu_set_ttbr0_cfg()
172 arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); in qcom_adreno_smmu_set_ttbr0_cfg()
178 struct arm_smmu_device *smmu, in qcom_adreno_smmu_alloc_context_bank() argument
192 count = smmu->num_context_banks; in qcom_adreno_smmu_alloc_context_bank()
195 return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); in qcom_adreno_smmu_alloc_context_bank()
198 static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu) in qcom_adreno_can_do_ttbr1() argument
200 const struct device_node *np = smmu->dev->of_node; in qcom_adreno_can_do_ttbr1()
202 if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2")) in qcom_adreno_can_do_ttbr1()
213 smmu_domain->cfg.flush_walk_prefer_tlbiasid = true; in qcom_adreno_smmu_init_context()
220 * All targets that use the qcom,adreno-smmu compatible string *should* in qcom_adreno_smmu_init_context()
221 * be AARCH64 stage 1 but double check because the arm-smmu code assumes in qcom_adreno_smmu_init_context()
224 if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) && in qcom_adreno_smmu_init_context()
225 (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && in qcom_adreno_smmu_init_context()
226 (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) in qcom_adreno_smmu_init_context()
227 pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; in qcom_adreno_smmu_init_context()
234 priv->cookie = smmu_domain; in qcom_adreno_smmu_init_context()
235 priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; in qcom_adreno_smmu_init_context()
236 priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; in qcom_adreno_smmu_init_context()
237 priv->get_fault_info = qcom_adreno_smmu_get_fault_info; in qcom_adreno_smmu_init_context()
238 priv->set_stall = qcom_adreno_smmu_set_stall; in qcom_adreno_smmu_init_context()
239 priv->resume_translation = qcom_adreno_smmu_resume_translation; in qcom_adreno_smmu_init_context()
248 { .compatible = "qcom,sc7180-mdss" },
249 { .compatible = "qcom,sc7180-mss-pil" },
250 { .compatible = "qcom,sc7280-mdss" },
251 { .compatible = "qcom,sc7280-mss-pil" },
252 { .compatible = "qcom,sc8180x-mdss" },
253 { .compatible = "qcom,sc8280xp-mdss" },
254 { .compatible = "qcom,sdm845-mdss" },
255 { .compatible = "qcom,sdm845-mss-pil" },
256 { .compatible = "qcom,sm6350-mdss" },
257 { .compatible = "qcom,sm6375-mdss" },
258 { .compatible = "qcom,sm8150-mdss" },
259 { .compatible = "qcom,sm8250-mdss" },
266 smmu_domain->cfg.flush_walk_prefer_tlbiasid = true; in qcom_smmu_init_context()
271 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) in qcom_smmu_cfg_probe() argument
273 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); in qcom_smmu_cfg_probe()
280 * Some platforms support more than the Arm SMMU architected maximum of in qcom_smmu_cfg_probe()
286 if (smmu->num_mapping_groups > 128) { in qcom_smmu_cfg_probe()
287 dev_notice(smmu->dev, "\tLimiting the stream matching groups to 128\n"); in qcom_smmu_cfg_probe()
288 smmu->num_mapping_groups = 128; in qcom_smmu_cfg_probe()
291 last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); in qcom_smmu_cfg_probe()
302 arm_smmu_gr0_write(smmu, last_s2cr, reg); in qcom_smmu_cfg_probe()
303 reg = arm_smmu_gr0_read(smmu, last_s2cr); in qcom_smmu_cfg_probe()
305 qsmmu->bypass_quirk = true; in qcom_smmu_cfg_probe()
306 qsmmu->bypass_cbndx = smmu->num_context_banks - 1; in qcom_smmu_cfg_probe()
308 set_bit(qsmmu->bypass_cbndx, smmu->context_map); in qcom_smmu_cfg_probe()
310 arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); in qcom_smmu_cfg_probe()
313 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg); in qcom_smmu_cfg_probe()
316 for (i = 0; i < smmu->num_mapping_groups; i++) { in qcom_smmu_cfg_probe()
317 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); in qcom_smmu_cfg_probe()
322 smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr); in qcom_smmu_cfg_probe()
323 smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); in qcom_smmu_cfg_probe()
324 smmu->smrs[i].valid = true; in qcom_smmu_cfg_probe()
326 smmu->s2crs[i].type = S2CR_TYPE_BYPASS; in qcom_smmu_cfg_probe()
327 smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; in qcom_smmu_cfg_probe()
328 smmu->s2crs[i].cbndx = 0xff; in qcom_smmu_cfg_probe()
335 static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) in qcom_smmu_write_s2cr() argument
337 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx; in qcom_smmu_write_s2cr()
338 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); in qcom_smmu_write_s2cr()
339 u32 cbndx = s2cr->cbndx; in qcom_smmu_write_s2cr()
340 u32 type = s2cr->type; in qcom_smmu_write_s2cr()
343 if (qsmmu->bypass_quirk) { in qcom_smmu_write_s2cr()
352 cbndx = qsmmu->bypass_cbndx; in qcom_smmu_write_s2cr()
366 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg); in qcom_smmu_write_s2cr()
367 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg); in qcom_smmu_write_s2cr()
378 static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) in qcom_sdm845_smmu500_reset() argument
382 arm_mmu500_reset(smmu); in qcom_sdm845_smmu500_reset()
385 * To address performance degradation in non-real time clients, in qcom_sdm845_smmu500_reset()
386 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards, in qcom_sdm845_smmu500_reset()
388 * call handlers to turn on/off the wait-for-safe logic. in qcom_sdm845_smmu500_reset()
392 dev_warn(smmu->dev, "Failed to turn off SAFE logic\n"); in qcom_sdm845_smmu500_reset()
440 static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, in qcom_smmu_create() argument
443 const struct device_node *np = smmu->dev->of_node; in qcom_smmu_create()
448 return ERR_PTR(-EINVAL); in qcom_smmu_create()
450 if (np && of_device_is_compatible(np, "qcom,adreno-smmu")) in qcom_smmu_create()
451 impl = data->adreno_impl; in qcom_smmu_create()
453 impl = data->impl; in qcom_smmu_create()
456 return smmu; in qcom_smmu_create()
460 return ERR_PTR(-EPROBE_DEFER); in qcom_smmu_create()
462 qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL); in qcom_smmu_create()
464 return ERR_PTR(-ENOMEM); in qcom_smmu_create()
466 qsmmu->smmu.impl = impl; in qcom_smmu_create()
467 qsmmu->cfg = data->cfg; in qcom_smmu_create()
469 return &qsmmu->smmu; in qcom_smmu_create()
484 * It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996,
500 * No need for adreno impl here. On sdm845 the Adreno SMMU is handled
501 * by the separate sdm845-smmu-v2 device.
513 * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need
514 * special handling and can not be covered by the qcom,smmu-500 entry.
517 { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data },
518 { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },
519 { .compatible = "qcom,qcm2290-smmu-500", .data = &qcom_smmu_500_impl0_data },
520 { .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data },
521 { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
522 { .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data },
523 { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
524 { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
525 { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
526 { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },
527 { .compatible = "qcom,sdm845-smmu-v2", .data = &qcom_smmu_v2_data },
528 { .compatible = "qcom,sdm845-smmu-500", .data = &sdm845_smmu_500_data },
529 { .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_500_impl0_data},
530 { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },
531 { .compatible = "qcom,sm6350-smmu-v2", .data = &qcom_smmu_v2_data },
532 { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },
533 { .compatible = "qcom,sm6375-smmu-v2", .data = &qcom_smmu_v2_data },
534 { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },
535 { .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data },
536 { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
537 { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
538 { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
539 { .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
545 { "LENOVO", "CB-01 ", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
546 { "QCOM ", "QCOMEDK2", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
551 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) in qcom_smmu_impl_init() argument
553 const struct device_node *np = smmu->dev->of_node; in qcom_smmu_impl_init()
560 return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data); in qcom_smmu_impl_init()
566 return qcom_smmu_create(smmu, match->data); in qcom_smmu_impl_init()
570 * qcom_smmu_impl_of_match[] table, and GPU per-process page- in qcom_smmu_impl_init()
573 WARN(of_device_is_compatible(np, "qcom,adreno-smmu"), in qcom_smmu_impl_init()
575 dev_name(smmu->dev)); in qcom_smmu_impl_init()
577 return smmu; in qcom_smmu_impl_init()