Lines Matching +full:32 +full:- +full:63

1 /* SPDX-License-Identifier: GPL-2.0-only */
94 /* CR1 cacheability fields don't quite follow the usual TCR-style encoding */
175 #define Q_IDX(llq, p)			((p) & ((1 << (llq)->max_n_shift) - 1))
176 #define Q_WRP(llq, p)			((p) & (1 << (llq)->max_n_shift))
179 #define Q_ENT(q, p)			((q)->base +			\
180 					 Q_IDX(&((q)->llq), p) *	\
181 					 (q)->ent_dwords)
220 #define STRTAB_STE_0_S1CDMAX		GENMASK_ULL(63, 59)
250 #define STRTAB_STE_2_VTCR		GENMASK_ULL(50, 32)
291 #define CTXDESC_CD_0_TCR_IPS		GENMASK_ULL(34, 32)
299 #define CTXDESC_CD_0_ASID		GENMASK_ULL(63, 48)
312 #define CMDQ_MAX_SZ_SHIFT		(Q_MAX_SZ_SHIFT - CMDQ_ENT_SZ_SHIFT)
332 #define CMDQ_PREFETCH_0_SID		GENMASK_ULL(63, 32)
334 #define CMDQ_PREFETCH_1_ADDR_MASK	GENMASK_ULL(63, 12)
337 #define CMDQ_CFGI_0_SID			GENMASK_ULL(63, 32)
344 #define CMDQ_TLBI_0_VMID		GENMASK_ULL(47, 32)
345 #define CMDQ_TLBI_0_ASID		GENMASK_ULL(63, 48)
349 #define CMDQ_TLBI_1_VA_MASK		GENMASK_ULL(63, 12)
353 #define CMDQ_ATC_0_SID			GENMASK_ULL(63, 32)
356 #define CMDQ_ATC_1_ADDR_MASK		GENMASK_ULL(63, 12)
359 #define CMDQ_PRI_0_SID			GENMASK_ULL(63, 32)
367 #define CMDQ_RESUME_0_SID		GENMASK_ULL(63, 32)
376 #define CMDQ_SYNC_0_MSIDATA		GENMASK_ULL(63, 32)
382 #define EVTQ_MAX_SZ_SHIFT		(Q_MAX_SZ_SHIFT - EVTQ_ENT_SZ_SHIFT)
393 #define EVTQ_0_SID			GENMASK_ULL(63, 32)
402 #define EVTQ_2_ADDR			GENMASK_ULL(63, 0)
408 #define PRIQ_MAX_SZ_SHIFT		(Q_MAX_SZ_SHIFT - PRIQ_ENT_SZ_SHIFT)
411 #define PRIQ_0_SSID			GENMASK_ULL(51, 32)
417 #define PRIQ_0_SSID_V			(1UL << 63)
420 #define PRIQ_1_ADDR_MASK		GENMASK_ULL(63, 12)
422 /* High-level queue structures */
440 	/* Command-specific fields */
570 /* High-level stream table and context descriptor structures */
787 	return -ENODEV;  in arm_smmu_master_enable_sva()
792 	return -ENODEV;  in arm_smmu_master_disable_sva()