Lines Matching refs:reg_width
687 int reg_width; member
701 .reg_width = 8,
709 .reg_width = 8,
717 .reg_width = 1,
725 .reg_width = 1,
732 .reg_width = 1,
739 .reg_width = 1,
746 .reg_width = 3,
755 .reg_width = 1,
762 .reg_width = 4,
770 .reg_width = 4,
778 .reg_width = 2,
786 .reg_width = 2,
794 .reg_width = 5,
802 .reg_width = 5,
810 .reg_width = 10,
818 .reg_width = 2,
826 .reg_width = 1,
833 .reg_width = 1,
840 .reg_width = 1,
847 .reg_width = 1,
854 .reg_width = 1,
861 .reg_width = 2,
869 .reg_width = 8,
878 .reg_width = 5,
887 .reg_width = 3,
896 .reg_width = 5,
904 .reg_width = 4,
912 .reg_width = 5,
920 .reg_width = 5,
928 .reg_width = 10,
937 .reg_width = 4,
946 .reg_width = 4,
955 .reg_width = 8,
965 .reg_width = 8,
974 .reg_width = 8,
982 .reg_width = 4,
990 .reg_width = 4,
998 .reg_width = 4,
1006 .reg_width = 4,
1014 .reg_width = 4,
1022 .reg_width = 4,
1030 .reg_width = 8,
1039 .reg_width = 1,
1047 .reg_width = 3,
1056 .reg_width = 1,
1064 .reg_width = 3,
1072 .reg_width = 8,
1080 .reg_width = 8,
1089 .reg_width = 8,
1099 .reg_width = 8,
1109 .reg_width = 5,
1119 .reg_width = 5,
1129 .reg_width = 8,
1139 .reg_width = 8,
1149 .reg_width = 8,
1159 .reg_width = 8,
1168 .reg_width = 4,
1178 .reg_width = 4,
1188 .reg_width = 8,
1196 .reg_width = 8,
1204 .reg_width = 8,
1212 .reg_width = 8,
1220 .reg_width = 8,
1229 .reg_width = 8,
1238 .reg_width = 8,
1248 .reg_width = 8,
1258 .reg_width = 8,
1268 .reg_width = 16,
1277 .reg_width = 16,
1285 .reg_width = 1,
1292 .reg_width = 16,
1301 .reg_width = 16,
1309 .reg_width = 16,
1317 .reg_width = 16,
1326 .reg_width = 16,
1334 .reg_width = 16,
1343 .reg_width = 16,
1351 .reg_width = 16,
1962 int reg_width = iqs7222_props[i].reg_width; in iqs7222_parse_props() local
1983 if (reg_width == 1) { in iqs7222_parse_props()
1993 if (reg_width == 1) { in iqs7222_parse_props()
2010 val_max = GENMASK(reg_width - 1, 0) * val_pitch; in iqs7222_parse_props()
2018 setup[reg_offset] &= ~GENMASK(reg_shift + reg_width - 1, in iqs7222_parse_props()