783 				  enum qib_ureg regno, int ctxt)  in qib_read_ureg32()  argument
788 		(dd->ureg_align * ctxt) + (dd->userbase ?  in qib_read_ureg32()
803 				  enum qib_ureg regno, u64 value, int ctxt)  in qib_write_ureg()  argument
810 			 dd->ureg_align * ctxt);  in qib_write_ureg()
815 			 dd->ureg_align * ctxt);  in qib_write_ureg()
872 				       const u16 regno, unsigned ctxt,  in qib_write_kreg_ctxt()  argument
875 	qib_write_kreg(dd, regno + ctxt, value);  in qib_write_kreg_ctxt()
2677 	if (cspec->rhdr_cpu[rcd->ctxt] != cpu) {  in qib_update_rhdrq_dca()
2680 		cspec->rhdr_cpu[rcd->ctxt] = cpu;  in qib_update_rhdrq_dca()
2681 		rmp = &dca_rcvhdr_reg_map[rcd->ctxt];  in qib_update_rhdrq_dca()
2686 			"Ctxt %d cpu %d dca %llx\n", rcd->ctxt, cpu,  in qib_update_rhdrq_dca()
3019 	u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt];  in adjust_rcv_timeout()
3032 	dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout;  in adjust_rcv_timeout()
3033 	qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout);  in adjust_rcv_timeout()
3155 		       (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt);  in qib_7322pintr()
3443 			unsigned ctxt;  in qib_setup_7322_interrupt()  local
3445 			ctxt = i - ARRAY_SIZE(irq_table);  in qib_setup_7322_interrupt()
3447 			arg = dd->rcd[ctxt];  in qib_setup_7322_interrupt()
3450 			if (qib_krcvq01_no_msi && ctxt < 2)  in qib_setup_7322_interrupt()
3455 			lsb = QIB_I_RCVAVAIL_LSB + ctxt;  in qib_setup_7322_interrupt()
3787 	u32 ctxt;  in qib_7322_clear_tids()  local
3793 	ctxt = rcd->ctxt;  in qib_7322_clear_tids()
3799 		 ctxt * dd->rcvtidcnt * sizeof(*tidbase));  in qib_7322_clear_tids()
4417 		qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);  in qib_update_7322_usrhead()
4418 	qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);  in qib_update_7322_usrhead()
4419 	qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);  in qib_update_7322_usrhead()
4426 	head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);  in qib_7322_hdrqempty()
4430 		tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);  in qib_7322_hdrqempty()
4458 			     int ctxt)  in rcvctrl_7322_mod()  argument
4479 	if (ctxt < 0) {  in rcvctrl_7322_mod()
4483 		mask = (1ULL << ctxt);  in rcvctrl_7322_mod()
4484 		rcd = dd->rcd[ctxt];  in rcvctrl_7322_mod()
4494 		qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt,  in rcvctrl_7322_mod()
4496 		qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt,  in rcvctrl_7322_mod()
4520 	if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) {  in rcvctrl_7322_mod()
4527 		val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);  in rcvctrl_7322_mod()
4528 		qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);  in rcvctrl_7322_mod()
4532 		val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);  in rcvctrl_7322_mod()
4533 		dd->rcd[ctxt]->head = val;  in rcvctrl_7322_mod()
4535 		if (ctxt < dd->first_user_ctxt)  in rcvctrl_7322_mod()
4537 		qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);  in rcvctrl_7322_mod()
4539 		dd->rcd[ctxt] && dd->rhdrhead_intr_off) {  in rcvctrl_7322_mod()
4541 		val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off;  in rcvctrl_7322_mod()
4542 		qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);  in rcvctrl_7322_mod()
4548 		if (ctxt >= 0) {  in rcvctrl_7322_mod()
4549 			qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0);  in rcvctrl_7322_mod()
4550 			qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0);  in rcvctrl_7322_mod()
4553 					       TIDFLOW_ERRBITS, ctxt);  in rcvctrl_7322_mod()
6291 			unsigned ctxt;  in write_7322_initregs()  local
6294 				ctxt = (i % n) * dd->num_pports + pidx;  in write_7322_initregs()
6296 				ctxt = (i % n) + 1;  in write_7322_initregs()
6298 				ctxt = ppd->hw_pidx;  in write_7322_initregs()
6299 			val |= ctxt << (5 * (i % 6));  in write_7322_initregs()
6978 	if (rcd->ctxt < NUM_IB_PORTS) {  in qib_7322_init_ctxt()
6981 			rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0;  in qib_7322_init_ctxt()
6989 			(rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt;  in qib_7322_init_ctxt()