Lines Matching full:x1
39 #define QIB_7322_Revision_R_Simulator_RMASK 0x1
42 #define QIB_7322_Revision_R_Emulation_RMASK 0x1
66 #define QIB_7322_Control_PCIECplQDiagEn_RMASK 0x1
69 #define QIB_7322_Control_PCIEPostQDiagEn_RMASK 0x1
72 #define QIB_7322_Control_SDmaDescFetchPriorityEn_RMASK 0x1
75 #define QIB_7322_Control_PCIERetryBufDiagEn_RMASK 0x1
76 #define QIB_7322_Control_FreezeMode_LSB 0x1
77 #define QIB_7322_Control_FreezeMode_MSB 0x1
78 #define QIB_7322_Control_FreezeMode_RMASK 0x1
81 #define QIB_7322_Control_SyncReset_RMASK 0x1
105 #define QIB_7322_IntMask_SDmaIntMask_1_RMASK 0x1
108 #define QIB_7322_IntMask_SDmaIntMask_0_RMASK 0x1
111 #define QIB_7322_IntMask_SDmaProgressIntMask_1_RMASK 0x1
114 #define QIB_7322_IntMask_SDmaProgressIntMask_0_RMASK 0x1
117 #define QIB_7322_IntMask_SDmaIdleIntMask_1_RMASK 0x1
120 #define QIB_7322_IntMask_SDmaIdleIntMask_0_RMASK 0x1
123 #define QIB_7322_IntMask_SDmaCleanupDoneMask_1_RMASK 0x1
126 #define QIB_7322_IntMask_SDmaCleanupDoneMask_0_RMASK 0x1
129 #define QIB_7322_IntMask_RcvUrg17IntMask_RMASK 0x1
132 #define QIB_7322_IntMask_RcvUrg16IntMask_RMASK 0x1
135 #define QIB_7322_IntMask_RcvUrg15IntMask_RMASK 0x1
138 #define QIB_7322_IntMask_RcvUrg14IntMask_RMASK 0x1
141 #define QIB_7322_IntMask_RcvUrg13IntMask_RMASK 0x1
144 #define QIB_7322_IntMask_RcvUrg12IntMask_RMASK 0x1
147 #define QIB_7322_IntMask_RcvUrg11IntMask_RMASK 0x1
150 #define QIB_7322_IntMask_RcvUrg10IntMask_RMASK 0x1
153 #define QIB_7322_IntMask_RcvUrg9IntMask_RMASK 0x1
156 #define QIB_7322_IntMask_RcvUrg8IntMask_RMASK 0x1
159 #define QIB_7322_IntMask_RcvUrg7IntMask_RMASK 0x1
162 #define QIB_7322_IntMask_RcvUrg6IntMask_RMASK 0x1
165 #define QIB_7322_IntMask_RcvUrg5IntMask_RMASK 0x1
168 #define QIB_7322_IntMask_RcvUrg4IntMask_RMASK 0x1
171 #define QIB_7322_IntMask_RcvUrg3IntMask_RMASK 0x1
174 #define QIB_7322_IntMask_RcvUrg2IntMask_RMASK 0x1
177 #define QIB_7322_IntMask_RcvUrg1IntMask_RMASK 0x1
180 #define QIB_7322_IntMask_RcvUrg0IntMask_RMASK 0x1
183 #define QIB_7322_IntMask_ErrIntMask_1_RMASK 0x1
186 #define QIB_7322_IntMask_ErrIntMask_0_RMASK 0x1
189 #define QIB_7322_IntMask_ErrIntMask_RMASK 0x1
192 #define QIB_7322_IntMask_AssertGPIOIntMask_RMASK 0x1
195 #define QIB_7322_IntMask_SendDoneIntMask_1_RMASK 0x1
198 #define QIB_7322_IntMask_SendDoneIntMask_0_RMASK 0x1
201 #define QIB_7322_IntMask_SendBufAvailIntMask_RMASK 0x1
204 #define QIB_7322_IntMask_RcvAvail17IntMask_RMASK 0x1
207 #define QIB_7322_IntMask_RcvAvail16IntMask_RMASK 0x1
210 #define QIB_7322_IntMask_RcvAvail15IntMask_RMASK 0x1
213 #define QIB_7322_IntMask_RcvAvail14IntMask_RMASK 0x1
216 #define QIB_7322_IntMask_RcvAvail13IntMask_RMASK 0x1
219 #define QIB_7322_IntMask_RcvAvail12IntMask_RMASK 0x1
222 #define QIB_7322_IntMask_RcvAvail11IntMask_RMASK 0x1
225 #define QIB_7322_IntMask_RcvAvail10IntMask_RMASK 0x1
228 #define QIB_7322_IntMask_RcvAvail9IntMask_RMASK 0x1
231 #define QIB_7322_IntMask_RcvAvail8IntMask_RMASK 0x1
234 #define QIB_7322_IntMask_RcvAvail7IntMask_RMASK 0x1
237 #define QIB_7322_IntMask_RcvAvail6IntMask_RMASK 0x1
240 #define QIB_7322_IntMask_RcvAvail5IntMask_RMASK 0x1
243 #define QIB_7322_IntMask_RcvAvail4IntMask_RMASK 0x1
246 #define QIB_7322_IntMask_RcvAvail3IntMask_RMASK 0x1
249 #define QIB_7322_IntMask_RcvAvail2IntMask_RMASK 0x1
250 #define QIB_7322_IntMask_RcvAvail1IntMask_LSB 0x1
251 #define QIB_7322_IntMask_RcvAvail1IntMask_MSB 0x1
252 #define QIB_7322_IntMask_RcvAvail1IntMask_RMASK 0x1
255 #define QIB_7322_IntMask_RcvAvail0IntMask_RMASK 0x1
261 #define QIB_7322_IntStatus_SDmaInt_1_RMASK 0x1
264 #define QIB_7322_IntStatus_SDmaInt_0_RMASK 0x1
267 #define QIB_7322_IntStatus_SDmaProgressInt_1_RMASK 0x1
270 #define QIB_7322_IntStatus_SDmaProgressInt_0_RMASK 0x1
273 #define QIB_7322_IntStatus_SDmaIdleInt_1_RMASK 0x1
276 #define QIB_7322_IntStatus_SDmaIdleInt_0_RMASK 0x1
279 #define QIB_7322_IntStatus_SDmaCleanupDone_1_RMASK 0x1
282 #define QIB_7322_IntStatus_SDmaCleanupDone_0_RMASK 0x1
285 #define QIB_7322_IntStatus_RcvUrg17_RMASK 0x1
288 #define QIB_7322_IntStatus_RcvUrg16_RMASK 0x1
291 #define QIB_7322_IntStatus_RcvUrg15_RMASK 0x1
294 #define QIB_7322_IntStatus_RcvUrg14_RMASK 0x1
297 #define QIB_7322_IntStatus_RcvUrg13_RMASK 0x1
300 #define QIB_7322_IntStatus_RcvUrg12_RMASK 0x1
303 #define QIB_7322_IntStatus_RcvUrg11_RMASK 0x1
306 #define QIB_7322_IntStatus_RcvUrg10_RMASK 0x1
309 #define QIB_7322_IntStatus_RcvUrg9_RMASK 0x1
312 #define QIB_7322_IntStatus_RcvUrg8_RMASK 0x1
315 #define QIB_7322_IntStatus_RcvUrg7_RMASK 0x1
318 #define QIB_7322_IntStatus_RcvUrg6_RMASK 0x1
321 #define QIB_7322_IntStatus_RcvUrg5_RMASK 0x1
324 #define QIB_7322_IntStatus_RcvUrg4_RMASK 0x1
327 #define QIB_7322_IntStatus_RcvUrg3_RMASK 0x1
330 #define QIB_7322_IntStatus_RcvUrg2_RMASK 0x1
333 #define QIB_7322_IntStatus_RcvUrg1_RMASK 0x1
336 #define QIB_7322_IntStatus_RcvUrg0_RMASK 0x1
339 #define QIB_7322_IntStatus_Err_1_RMASK 0x1
342 #define QIB_7322_IntStatus_Err_0_RMASK 0x1
345 #define QIB_7322_IntStatus_Err_RMASK 0x1
348 #define QIB_7322_IntStatus_AssertGPIO_RMASK 0x1
351 #define QIB_7322_IntStatus_SendDone_1_RMASK 0x1
354 #define QIB_7322_IntStatus_SendDone_0_RMASK 0x1
357 #define QIB_7322_IntStatus_SendBufAvail_RMASK 0x1
360 #define QIB_7322_IntStatus_RcvAvail17_RMASK 0x1
363 #define QIB_7322_IntStatus_RcvAvail16_RMASK 0x1
366 #define QIB_7322_IntStatus_RcvAvail15_RMASK 0x1
369 #define QIB_7322_IntStatus_RcvAvail14_RMASK 0x1
372 #define QIB_7322_IntStatus_RcvAvail13_RMASK 0x1
375 #define QIB_7322_IntStatus_RcvAvail12_RMASK 0x1
378 #define QIB_7322_IntStatus_RcvAvail11_RMASK 0x1
381 #define QIB_7322_IntStatus_RcvAvail10_RMASK 0x1
384 #define QIB_7322_IntStatus_RcvAvail9_RMASK 0x1
387 #define QIB_7322_IntStatus_RcvAvail8_RMASK 0x1
390 #define QIB_7322_IntStatus_RcvAvail7_RMASK 0x1
393 #define QIB_7322_IntStatus_RcvAvail6_RMASK 0x1
396 #define QIB_7322_IntStatus_RcvAvail5_RMASK 0x1
399 #define QIB_7322_IntStatus_RcvAvail4_RMASK 0x1
402 #define QIB_7322_IntStatus_RcvAvail3_RMASK 0x1
405 #define QIB_7322_IntStatus_RcvAvail2_RMASK 0x1
406 #define QIB_7322_IntStatus_RcvAvail1_LSB 0x1
407 #define QIB_7322_IntStatus_RcvAvail1_MSB 0x1
408 #define QIB_7322_IntStatus_RcvAvail1_RMASK 0x1
411 #define QIB_7322_IntStatus_RcvAvail0_RMASK 0x1
417 #define QIB_7322_IntClear_SDmaIntClear_1_RMASK 0x1
420 #define QIB_7322_IntClear_SDmaIntClear_0_RMASK 0x1
423 #define QIB_7322_IntClear_SDmaProgressIntClear_1_RMASK 0x1
426 #define QIB_7322_IntClear_SDmaProgressIntClear_0_RMASK 0x1
429 #define QIB_7322_IntClear_SDmaIdleIntClear_1_RMASK 0x1
432 #define QIB_7322_IntClear_SDmaIdleIntClear_0_RMASK 0x1
435 #define QIB_7322_IntClear_SDmaCleanupDoneClear_1_RMASK 0x1
438 #define QIB_7322_IntClear_SDmaCleanupDoneClear_0_RMASK 0x1
441 #define QIB_7322_IntClear_RcvUrg17IntClear_RMASK 0x1
444 #define QIB_7322_IntClear_RcvUrg16IntClear_RMASK 0x1
447 #define QIB_7322_IntClear_RcvUrg15IntClear_RMASK 0x1
450 #define QIB_7322_IntClear_RcvUrg14IntClear_RMASK 0x1
453 #define QIB_7322_IntClear_RcvUrg13IntClear_RMASK 0x1
456 #define QIB_7322_IntClear_RcvUrg12IntClear_RMASK 0x1
459 #define QIB_7322_IntClear_RcvUrg11IntClear_RMASK 0x1
462 #define QIB_7322_IntClear_RcvUrg10IntClear_RMASK 0x1
465 #define QIB_7322_IntClear_RcvUrg9IntClear_RMASK 0x1
468 #define QIB_7322_IntClear_RcvUrg8IntClear_RMASK 0x1
471 #define QIB_7322_IntClear_RcvUrg7IntClear_RMASK 0x1
474 #define QIB_7322_IntClear_RcvUrg6IntClear_RMASK 0x1
477 #define QIB_7322_IntClear_RcvUrg5IntClear_RMASK 0x1
480 #define QIB_7322_IntClear_RcvUrg4IntClear_RMASK 0x1
483 #define QIB_7322_IntClear_RcvUrg3IntClear_RMASK 0x1
486 #define QIB_7322_IntClear_RcvUrg2IntClear_RMASK 0x1
489 #define QIB_7322_IntClear_RcvUrg1IntClear_RMASK 0x1
492 #define QIB_7322_IntClear_RcvUrg0IntClear_RMASK 0x1
495 #define QIB_7322_IntClear_ErrIntClear_1_RMASK 0x1
498 #define QIB_7322_IntClear_ErrIntClear_0_RMASK 0x1
501 #define QIB_7322_IntClear_ErrIntClear_RMASK 0x1
504 #define QIB_7322_IntClear_AssertGPIOIntClear_RMASK 0x1
507 #define QIB_7322_IntClear_SendDoneIntClear_1_RMASK 0x1
510 #define QIB_7322_IntClear_SendDoneIntClear_0_RMASK 0x1
513 #define QIB_7322_IntClear_SendBufAvailIntClear_RMASK 0x1
516 #define QIB_7322_IntClear_RcvAvail17IntClear_RMASK 0x1
519 #define QIB_7322_IntClear_RcvAvail16IntClear_RMASK 0x1
522 #define QIB_7322_IntClear_RcvAvail15IntClear_RMASK 0x1
525 #define QIB_7322_IntClear_RcvAvail14IntClear_RMASK 0x1
528 #define QIB_7322_IntClear_RcvAvail13IntClear_RMASK 0x1
531 #define QIB_7322_IntClear_RcvAvail12IntClear_RMASK 0x1
534 #define QIB_7322_IntClear_RcvAvail11IntClear_RMASK 0x1
537 #define QIB_7322_IntClear_RcvAvail10IntClear_RMASK 0x1
540 #define QIB_7322_IntClear_RcvAvail9IntClear_RMASK 0x1
543 #define QIB_7322_IntClear_RcvAvail8IntClear_RMASK 0x1
546 #define QIB_7322_IntClear_RcvAvail7IntClear_RMASK 0x1
549 #define QIB_7322_IntClear_RcvAvail6IntClear_RMASK 0x1
552 #define QIB_7322_IntClear_RcvAvail5IntClear_RMASK 0x1
555 #define QIB_7322_IntClear_RcvAvail4IntClear_RMASK 0x1
558 #define QIB_7322_IntClear_RcvAvail3IntClear_RMASK 0x1
561 #define QIB_7322_IntClear_RcvAvail2IntClear_RMASK 0x1
562 #define QIB_7322_IntClear_RcvAvail1IntClear_LSB 0x1
563 #define QIB_7322_IntClear_RcvAvail1IntClear_MSB 0x1
564 #define QIB_7322_IntClear_RcvAvail1IntClear_RMASK 0x1
567 #define QIB_7322_IntClear_RcvAvail0IntClear_RMASK 0x1
573 #define QIB_7322_ErrMask_ResetNegatedMask_RMASK 0x1
576 #define QIB_7322_ErrMask_HardwareErrMask_RMASK 0x1
579 #define QIB_7322_ErrMask_InvalidAddrErrMask_RMASK 0x1
582 #define QIB_7322_ErrMask_SDmaVL15ErrMask_RMASK 0x1
585 #define QIB_7322_ErrMask_SBufVL15MisUseErrMask_RMASK 0x1
588 #define QIB_7322_ErrMask_InvalidEEPCmdMask_RMASK 0x1
591 #define QIB_7322_ErrMask_RcvContextShareErrMask_RMASK 0x1
594 #define QIB_7322_ErrMask_SendVLMismatchErrMask_RMASK 0x1
597 #define QIB_7322_ErrMask_SendArmLaunchErrMask_RMASK 0x1
600 #define QIB_7322_ErrMask_SendSpecialTriggerErrMask_RMASK 0x1
603 #define QIB_7322_ErrMask_SDmaWrongPortErrMask_RMASK 0x1
606 #define QIB_7322_ErrMask_SDmaBufMaskDuplicateErrMask_RMASK 0x1
609 #define QIB_7322_ErrMask_RcvHdrFullErrMask_RMASK 0x1
612 #define QIB_7322_ErrMask_RcvEgrFullErrMask_RMASK 0x1
618 #define QIB_7322_ErrStatus_ResetNegated_RMASK 0x1
621 #define QIB_7322_ErrStatus_HardwareErr_RMASK 0x1
624 #define QIB_7322_ErrStatus_InvalidAddrErr_RMASK 0x1
627 #define QIB_7322_ErrStatus_SDmaVL15Err_RMASK 0x1
630 #define QIB_7322_ErrStatus_SBufVL15MisUseErr_RMASK 0x1
633 #define QIB_7322_ErrStatus_InvalidEEPCmdErr_RMASK 0x1
636 #define QIB_7322_ErrStatus_RcvContextShareErr_RMASK 0x1
639 #define QIB_7322_ErrStatus_SendVLMismatchErr_RMASK 0x1
642 #define QIB_7322_ErrStatus_SendArmLaunchErr_RMASK 0x1
645 #define QIB_7322_ErrStatus_SendSpecialTriggerErr_RMASK 0x1
648 #define QIB_7322_ErrStatus_SDmaWrongPortErr_RMASK 0x1
651 #define QIB_7322_ErrStatus_SDmaBufMaskDuplicateErr_RMASK 0x1
654 #define QIB_7322_ErrStatus_RcvHdrFullErr_RMASK 0x1
657 #define QIB_7322_ErrStatus_RcvEgrFullErr_RMASK 0x1
663 #define QIB_7322_ErrClear_ResetNegatedClear_RMASK 0x1
666 #define QIB_7322_ErrClear_HardwareErrClear_RMASK 0x1
669 #define QIB_7322_ErrClear_InvalidAddrErrClear_RMASK 0x1
672 #define QIB_7322_ErrClear_SDmaVL15ErrClear_RMASK 0x1
675 #define QIB_7322_ErrClear_SBufVL15MisUseErrClear_RMASK 0x1
678 #define QIB_7322_ErrClear_InvalidEEPCmdErrClear_RMASK 0x1
681 #define QIB_7322_ErrClear_RcvContextShareErrClear_RMASK 0x1
684 #define QIB_7322_ErrClear_SendVLMismatchErrMask_RMASK 0x1
687 #define QIB_7322_ErrClear_SendArmLaunchErrClear_RMASK 0x1
690 #define QIB_7322_ErrClear_SendSpecialTriggerErrClear_RMASK 0x1
693 #define QIB_7322_ErrClear_SDmaWrongPortErrClear_RMASK 0x1
696 #define QIB_7322_ErrClear_SDmaBufMaskDuplicateErrClear_RMASK 0x1
699 #define QIB_7322_ErrClear_RcvHdrFullErrClear_RMASK 0x1
702 #define QIB_7322_ErrClear_RcvEgrFullErrClear_RMASK 0x1
708 #define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_1_RMASK 0x1
711 #define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_0_RMASK 0x1
714 #define QIB_7322_HwErrMask_PCIESerdesPClkNotDetectMask_RMASK 0x1
717 #define QIB_7322_HwErrMask_PowerOnBISTFailedMask_RMASK 0x1
720 #define QIB_7322_HwErrMask_TempsenseTholdReachedMask_RMASK 0x1
723 #define QIB_7322_HwErrMask_MemoryErrMask_RMASK 0x1
726 #define QIB_7322_HwErrMask_pcie_phy_txParityErr_RMASK 0x1
732 #define QIB_7322_HwErrMask_PcieCplTimeoutMask_RMASK 0x1
735 #define QIB_7322_HwErrMask_PciePoisonedTLPMask_RMASK 0x1
738 #define QIB_7322_HwErrMask_SDmaMemReadErrMask_1_RMASK 0x1
741 #define QIB_7322_HwErrMask_SDmaMemReadErrMask_0_RMASK 0x1
744 #define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_1_RMASK 0x1
747 #define QIB_7322_HwErrMask_IBCBusToSPCParityErrMask_1_RMASK 0x1
750 #define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_0_RMASK 0x1
753 #define QIB_7322_HwErrMask_statusValidNoEopMask_RMASK 0x1
756 #define QIB_7322_HwErrMask_LATriggeredMask_RMASK 0x1
762 #define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_1_RMASK 0x1
765 #define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_0_RMASK 0x1
768 #define QIB_7322_HwErrStatus_PCIESerdesPClkNotDetect_RMASK 0x1
771 #define QIB_7322_HwErrStatus_PowerOnBISTFailed_RMASK 0x1
774 #define QIB_7322_HwErrStatus_TempsenseTholdReached_RMASK 0x1
777 #define QIB_7322_HwErrStatus_MemoryErr_RMASK 0x1
780 #define QIB_7322_HwErrStatus_pcie_phy_txParityErr_RMASK 0x1
786 #define QIB_7322_HwErrStatus_PcieCplTimeout_RMASK 0x1
789 #define QIB_7322_HwErrStatus_PciePoisonedTLP_RMASK 0x1
792 #define QIB_7322_HwErrStatus_SDmaMemReadErr_1_RMASK 0x1
795 #define QIB_7322_HwErrStatus_SDmaMemReadErr_0_RMASK 0x1
798 #define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_1_RMASK 0x1
801 #define QIB_7322_HwErrStatus_IBCBusToSPCParityErr_1_RMASK 0x1
804 #define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_0_RMASK 0x1
807 #define QIB_7322_HwErrStatus_statusValidNoEop_RMASK 0x1
810 #define QIB_7322_HwErrStatus_LATriggered_RMASK 0x1
816 #define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_1_RMASK 0x1
819 #define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_0_RMASK 0x1
822 #define QIB_7322_HwErrClear_PCIESerdesPClkNotDetectClear_RMASK 0x1
825 #define QIB_7322_HwErrClear_PowerOnBISTFailedClear_RMASK 0x1
828 #define QIB_7322_HwErrClear_TempsenseTholdReachedClear_RMASK 0x1
831 #define QIB_7322_HwErrClear_MemoryErrClear_RMASK 0x1
834 #define QIB_7322_HwErrClear_pcie_phy_txParityErr_RMASK 0x1
840 #define QIB_7322_HwErrClear_PcieCplTimeoutClear_RMASK 0x1
843 #define QIB_7322_HwErrClear_PciePoisonedTLPClear_RMASK 0x1
846 #define QIB_7322_HwErrClear_SDmaMemReadErrClear_1_RMASK 0x1
849 #define QIB_7322_HwErrClear_SDmaMemReadErrClear_0_RMASK 0x1
852 #define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_1_RMASK 0x1
855 #define QIB_7322_HwErrClear_IBCBusToSPCParityErrClear_1_RMASK 0x1
858 #define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_0_RMASK 0x1
861 #define QIB_7322_HwErrClear_statusValidNoEopClear_RMASK 0x1
864 #define QIB_7322_HwErrClear_LATriggeredClear_RMASK 0x1
870 #define QIB_7322_HwDiagCtrl_Diagnostic_RMASK 0x1
873 #define QIB_7322_HwDiagCtrl_CounterWrEnable_RMASK 0x1
876 #define QIB_7322_HwDiagCtrl_CounterDisable_RMASK 0x1
882 #define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_1_RMASK 0x1
885 #define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_1_RMASK 0x1
888 #define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_0_RMASK 0x1
891 #define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_0_RMASK 0x1
900 #define QIB_7322_EXTStatus_MemBISTDisabled_RMASK 0x1
903 #define QIB_7322_EXTStatus_MemBISTEndTest_RMASK 0x1
915 #define QIB_7322_EXTCtrl_LEDPort1GreenOn_RMASK 0x1
918 #define QIB_7322_EXTCtrl_LEDPort1YellowOn_RMASK 0x1
919 #define QIB_7322_EXTCtrl_LEDPort0GreenOn_LSB 0x1
920 #define QIB_7322_EXTCtrl_LEDPort0GreenOn_MSB 0x1
921 #define QIB_7322_EXTCtrl_LEDPort0GreenOn_RMASK 0x1
924 #define QIB_7322_EXTCtrl_LEDPort0YellowOn_RMASK 0x1
945 #define QIB_7322_RcvCtrl_TailUpd_RMASK 0x1
951 #define QIB_7322_RcvCtrl_TidFlowEnable_RMASK 0x1
1002 #define QIB_7322_active_feature_mask_Port1_QDR_Enabled_RMASK 0x1
1005 #define QIB_7322_active_feature_mask_Port1_DDR_Enabled_RMASK 0x1
1008 #define QIB_7322_active_feature_mask_Port1_SDR_Enabled_RMASK 0x1
1011 #define QIB_7322_active_feature_mask_Port0_QDR_Enabled_RMASK 0x1
1012 #define QIB_7322_active_feature_mask_Port0_DDR_Enabled_LSB 0x1
1013 #define QIB_7322_active_feature_mask_Port0_DDR_Enabled_MSB 0x1
1014 #define QIB_7322_active_feature_mask_Port0_DDR_Enabled_RMASK 0x1
1017 #define QIB_7322_active_feature_mask_Port0_SDR_Enabled_RMASK 0x1
1023 #define QIB_7322_SendCtrl_Disarm_RMASK 0x1
1026 #define QIB_7322_SendCtrl_SendBufAvailPad64Byte_RMASK 0x1
1035 #define QIB_7322_SendCtrl_SpecialTriggerEn_RMASK 0x1
1038 #define QIB_7322_SendCtrl_SendBufAvailUpd_RMASK 0x1
1039 #define QIB_7322_SendCtrl_SendIntBufAvail_LSB 0x1
1040 #define QIB_7322_SendCtrl_SendIntBufAvail_MSB 0x1
1041 #define QIB_7322_SendCtrl_SendIntBufAvail_RMASK 0x1
1102 #define QIB_7322_ahb_access_ctrl_sw_sel_ahb_trgt_LSB 0x1
1107 #define QIB_7322_ahb_access_ctrl_sw_ahb_sel_RMASK 0x1
1116 #define QIB_7322_ahb_transaction_reg_ahb_rdy_RMASK 0x1
1119 #define QIB_7322_ahb_transaction_reg_ahb_req_err_RMASK 0x1
1122 #define QIB_7322_ahb_transaction_reg_write_not_read_RMASK 0x1
1131 #define QIB_7322_SPC_JTAG_ACCESS_REG_SPC_JTAG_ACCESS_EN_RMASK 0x1
1140 #define QIB_7322_SPC_JTAG_ACCESS_REG_tdi_RMASK 0x1
1141 #define QIB_7322_SPC_JTAG_ACCESS_REG_tdo_LSB 0x1
1142 #define QIB_7322_SPC_JTAG_ACCESS_REG_tdo_MSB 0x1
1143 #define QIB_7322_SPC_JTAG_ACCESS_REG_tdo_RMASK 0x1
1146 #define QIB_7322_SPC_JTAG_ACCESS_REG_rdy_RMASK 0x1
1215 #define QIB_7322_DCACtrlA_SendDMAHead1DCAEnable_RMASK 0x1
1218 #define QIB_7322_DCACtrlA_SendDMAHead0DCAEnable_RMASK 0x1
1221 #define QIB_7322_DCACtrlA_RcvTailUpdDCAEnable_RMASK 0x1
1222 #define QIB_7322_DCACtrlA_EagerDCAEnable_LSB 0x1
1223 #define QIB_7322_DCACtrlA_EagerDCAEnable_MSB 0x1
1224 #define QIB_7322_DCACtrlA_EagerDCAEnable_RMASK 0x1
1227 #define QIB_7322_DCACtrlA_RcvHdrqDCAEnable_RMASK 0x1
1374 #define QIB_7322_ErrMask_0_IBStatusChangedMask_RMASK 0x1
1377 #define QIB_7322_ErrMask_0_SHeadersErrMask_RMASK 0x1
1380 #define QIB_7322_ErrMask_0_VL15BufMisuseErrMask_RMASK 0x1
1383 #define QIB_7322_ErrMask_0_SDmaHaltErrMask_RMASK 0x1
1386 #define QIB_7322_ErrMask_0_SDmaDescAddrMisalignErrMask_RMASK 0x1
1389 #define QIB_7322_ErrMask_0_SDmaUnexpDataErrMask_RMASK 0x1
1392 #define QIB_7322_ErrMask_0_SDmaMissingDwErrMask_RMASK 0x1
1395 #define QIB_7322_ErrMask_0_SDmaDwEnErrMask_RMASK 0x1
1398 #define QIB_7322_ErrMask_0_SDmaRpyTagErrMask_RMASK 0x1
1401 #define QIB_7322_ErrMask_0_SDma1stDescErrMask_RMASK 0x1
1404 #define QIB_7322_ErrMask_0_SDmaBaseErrMask_RMASK 0x1
1407 #define QIB_7322_ErrMask_0_SDmaTailOutOfBoundErrMask_RMASK 0x1
1410 #define QIB_7322_ErrMask_0_SDmaOutOfBoundErrMask_RMASK 0x1
1413 #define QIB_7322_ErrMask_0_SDmaGenMismatchErrMask_RMASK 0x1
1416 #define QIB_7322_ErrMask_0_SendBufMisuseErrMask_RMASK 0x1
1419 #define QIB_7322_ErrMask_0_SendUnsupportedVLErrMask_RMASK 0x1
1422 #define QIB_7322_ErrMask_0_SendUnexpectedPktNumErrMask_RMASK 0x1
1425 #define QIB_7322_ErrMask_0_SendDroppedDataPktErrMask_RMASK 0x1
1428 #define QIB_7322_ErrMask_0_SendDroppedSmpPktErrMask_RMASK 0x1
1431 #define QIB_7322_ErrMask_0_SendPktLenErrMask_RMASK 0x1
1434 #define QIB_7322_ErrMask_0_SendUnderRunErrMask_RMASK 0x1
1437 #define QIB_7322_ErrMask_0_SendMaxPktLenErrMask_RMASK 0x1
1440 #define QIB_7322_ErrMask_0_SendMinPktLenErrMask_RMASK 0x1
1443 #define QIB_7322_ErrMask_0_RcvIBLostLinkErrMask_RMASK 0x1
1446 #define QIB_7322_ErrMask_0_RcvHdrErrMask_RMASK 0x1
1449 #define QIB_7322_ErrMask_0_RcvHdrLenErrMask_RMASK 0x1
1452 #define QIB_7322_ErrMask_0_RcvBadTidErrMask_RMASK 0x1
1455 #define QIB_7322_ErrMask_0_RcvBadVersionErrMask_RMASK 0x1
1458 #define QIB_7322_ErrMask_0_RcvIBFlowErrMask_RMASK 0x1
1461 #define QIB_7322_ErrMask_0_RcvEBPErrMask_RMASK 0x1
1464 #define QIB_7322_ErrMask_0_RcvUnsupportedVLErrMask_RMASK 0x1
1467 #define QIB_7322_ErrMask_0_RcvUnexpectedCharErrMask_RMASK 0x1
1470 #define QIB_7322_ErrMask_0_RcvShortPktLenErrMask_RMASK 0x1
1473 #define QIB_7322_ErrMask_0_RcvLongPktLenErrMask_RMASK 0x1
1476 #define QIB_7322_ErrMask_0_RcvMaxPktLenErrMask_RMASK 0x1
1479 #define QIB_7322_ErrMask_0_RcvMinPktLenErrMask_RMASK 0x1
1482 #define QIB_7322_ErrMask_0_RcvICRCErrMask_RMASK 0x1
1483 #define QIB_7322_ErrMask_0_RcvVCRCErrMask_LSB 0x1
1484 #define QIB_7322_ErrMask_0_RcvVCRCErrMask_MSB 0x1
1485 #define QIB_7322_ErrMask_0_RcvVCRCErrMask_RMASK 0x1
1488 #define QIB_7322_ErrMask_0_RcvFormatErrMask_RMASK 0x1
1494 #define QIB_7322_ErrStatus_0_IBStatusChanged_RMASK 0x1
1497 #define QIB_7322_ErrStatus_0_SHeadersErr_RMASK 0x1
1500 #define QIB_7322_ErrStatus_0_VL15BufMisuseErr_RMASK 0x1
1503 #define QIB_7322_ErrStatus_0_SDmaHaltErr_RMASK 0x1
1506 #define QIB_7322_ErrStatus_0_SDmaDescAddrMisalignErr_RMASK 0x1
1509 #define QIB_7322_ErrStatus_0_SDmaUnexpDataErr_RMASK 0x1
1512 #define QIB_7322_ErrStatus_0_SDmaMissingDwErr_RMASK 0x1
1515 #define QIB_7322_ErrStatus_0_SDmaDwEnErr_RMASK 0x1
1518 #define QIB_7322_ErrStatus_0_SDmaRpyTagErr_RMASK 0x1
1521 #define QIB_7322_ErrStatus_0_SDma1stDescErr_RMASK 0x1
1524 #define QIB_7322_ErrStatus_0_SDmaBaseErr_RMASK 0x1
1527 #define QIB_7322_ErrStatus_0_SDmaTailOutOfBoundErr_RMASK 0x1
1530 #define QIB_7322_ErrStatus_0_SDmaOutOfBoundErr_RMASK 0x1
1533 #define QIB_7322_ErrStatus_0_SDmaGenMismatchErr_RMASK 0x1
1536 #define QIB_7322_ErrStatus_0_SendBufMisuseErr_RMASK 0x1
1539 #define QIB_7322_ErrStatus_0_SendUnsupportedVLErr_RMASK 0x1
1542 #define QIB_7322_ErrStatus_0_SendUnexpectedPktNumErr_RMASK 0x1
1545 #define QIB_7322_ErrStatus_0_SendDroppedDataPktErr_RMASK 0x1
1548 #define QIB_7322_ErrStatus_0_SendDroppedSmpPktErr_RMASK 0x1
1551 #define QIB_7322_ErrStatus_0_SendPktLenErr_RMASK 0x1
1554 #define QIB_7322_ErrStatus_0_SendUnderRunErr_RMASK 0x1
1557 #define QIB_7322_ErrStatus_0_SendMaxPktLenErr_RMASK 0x1
1560 #define QIB_7322_ErrStatus_0_SendMinPktLenErr_RMASK 0x1
1563 #define QIB_7322_ErrStatus_0_RcvIBLostLinkErr_RMASK 0x1
1566 #define QIB_7322_ErrStatus_0_RcvHdrErr_RMASK 0x1
1569 #define QIB_7322_ErrStatus_0_RcvHdrLenErr_RMASK 0x1
1572 #define QIB_7322_ErrStatus_0_RcvBadTidErr_RMASK 0x1
1575 #define QIB_7322_ErrStatus_0_RcvBadVersionErr_RMASK 0x1
1578 #define QIB_7322_ErrStatus_0_RcvIBFlowErr_RMASK 0x1
1581 #define QIB_7322_ErrStatus_0_RcvEBPErr_RMASK 0x1
1584 #define QIB_7322_ErrStatus_0_RcvUnsupportedVLErr_RMASK 0x1
1587 #define QIB_7322_ErrStatus_0_RcvUnexpectedCharErr_RMASK 0x1
1590 #define QIB_7322_ErrStatus_0_RcvShortPktLenErr_RMASK 0x1
1593 #define QIB_7322_ErrStatus_0_RcvLongPktLenErr_RMASK 0x1
1596 #define QIB_7322_ErrStatus_0_RcvMaxPktLenErr_RMASK 0x1
1599 #define QIB_7322_ErrStatus_0_RcvMinPktLenErr_RMASK 0x1
1602 #define QIB_7322_ErrStatus_0_RcvICRCErr_RMASK 0x1
1603 #define QIB_7322_ErrStatus_0_RcvVCRCErr_LSB 0x1
1604 #define QIB_7322_ErrStatus_0_RcvVCRCErr_MSB 0x1
1605 #define QIB_7322_ErrStatus_0_RcvVCRCErr_RMASK 0x1
1608 #define QIB_7322_ErrStatus_0_RcvFormatErr_RMASK 0x1
1614 #define QIB_7322_ErrClear_0_IBStatusChangedClear_RMASK 0x1
1617 #define QIB_7322_ErrClear_0_SHeadersErrClear_RMASK 0x1
1620 #define QIB_7322_ErrClear_0_VL15BufMisuseErrClear_RMASK 0x1
1623 #define QIB_7322_ErrClear_0_SDmaHaltErrClear_RMASK 0x1
1626 #define QIB_7322_ErrClear_0_SDmaDescAddrMisalignErrClear_RMASK 0x1
1629 #define QIB_7322_ErrClear_0_SDmaUnexpDataErrClear_RMASK 0x1
1632 #define QIB_7322_ErrClear_0_SDmaMissingDwErrClear_RMASK 0x1
1635 #define QIB_7322_ErrClear_0_SDmaDwEnErrClear_RMASK 0x1
1638 #define QIB_7322_ErrClear_0_SDmaRpyTagErrClear_RMASK 0x1
1641 #define QIB_7322_ErrClear_0_SDma1stDescErrClear_RMASK 0x1
1644 #define QIB_7322_ErrClear_0_SDmaBaseErrClear_RMASK 0x1
1647 #define QIB_7322_ErrClear_0_SDmaTailOutOfBoundErrClear_RMASK 0x1
1650 #define QIB_7322_ErrClear_0_SDmaOutOfBoundErrClear_RMASK 0x1
1653 #define QIB_7322_ErrClear_0_SDmaGenMismatchErrClear_RMASK 0x1
1656 #define QIB_7322_ErrClear_0_SendBufMisuseErrClear_RMASK 0x1
1659 #define QIB_7322_ErrClear_0_SendUnsupportedVLErrClear_RMASK 0x1
1662 #define QIB_7322_ErrClear_0_SendUnexpectedPktNumErrClear_RMASK 0x1
1665 #define QIB_7322_ErrClear_0_SendDroppedDataPktErrClear_RMASK 0x1
1668 #define QIB_7322_ErrClear_0_SendDroppedSmpPktErrClear_RMASK 0x1
1671 #define QIB_7322_ErrClear_0_SendPktLenErrClear_RMASK 0x1
1674 #define QIB_7322_ErrClear_0_SendUnderRunErrClear_RMASK 0x1
1677 #define QIB_7322_ErrClear_0_SendMaxPktLenErrClear_RMASK 0x1
1680 #define QIB_7322_ErrClear_0_SendMinPktLenErrClear_RMASK 0x1
1683 #define QIB_7322_ErrClear_0_RcvIBLostLinkErrClear_RMASK 0x1
1686 #define QIB_7322_ErrClear_0_RcvHdrErrClear_RMASK 0x1
1689 #define QIB_7322_ErrClear_0_RcvHdrLenErrClear_RMASK 0x1
1692 #define QIB_7322_ErrClear_0_RcvBadTidErrClear_RMASK 0x1
1695 #define QIB_7322_ErrClear_0_RcvBadVersionErrClear_RMASK 0x1
1698 #define QIB_7322_ErrClear_0_RcvIBFlowErrClear_RMASK 0x1
1701 #define QIB_7322_ErrClear_0_RcvEBPErrClear_RMASK 0x1
1704 #define QIB_7322_ErrClear_0_RcvUnsupportedVLErrClear_RMASK 0x1
1707 #define QIB_7322_ErrClear_0_RcvUnexpectedCharErrClear_RMASK 0x1
1710 #define QIB_7322_ErrClear_0_RcvShortPktLenErrClear_RMASK 0x1
1713 #define QIB_7322_ErrClear_0_RcvLongPktLenErrClear_RMASK 0x1
1716 #define QIB_7322_ErrClear_0_RcvMaxPktLenErrClear_RMASK 0x1
1719 #define QIB_7322_ErrClear_0_RcvMinPktLenErrClear_RMASK 0x1
1722 #define QIB_7322_ErrClear_0_RcvICRCErrClear_RMASK 0x1
1723 #define QIB_7322_ErrClear_0_RcvVCRCErrClear_LSB 0x1
1724 #define QIB_7322_ErrClear_0_RcvVCRCErrClear_MSB 0x1
1725 #define QIB_7322_ErrClear_0_RcvVCRCErrClear_RMASK 0x1
1728 #define QIB_7322_ErrClear_0_RcvFormatErrClear_RMASK 0x1
1734 #define QIB_7322_TXEStatus_0_TXE_IBC_Idle_RMASK 0x1
1737 #define QIB_7322_TXEStatus_0_RmFifoEmpty_RMASK 0x1
1740 #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL15_RMASK 0x1
1743 #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL7_RMASK 0x1
1746 #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL6_RMASK 0x1
1749 #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL5_RMASK 0x1
1752 #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL4_RMASK 0x1
1755 #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL3_RMASK 0x1
1758 #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL2_RMASK 0x1
1759 #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL1_LSB 0x1
1760 #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL1_MSB 0x1
1761 #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL1_RMASK 0x1
1764 #define QIB_7322_TXEStatus_0_LaFifoEmpty_VL0_RMASK 0x1
1770 #define QIB_7322_RcvCtrl_0_RcvResetCredit_RMASK 0x1
1773 #define QIB_7322_RcvCtrl_0_RcvPartitionKeyDisable_RMASK 0x1
1776 #define QIB_7322_RcvCtrl_0_RcvQPMapEnable_RMASK 0x1
1779 #define QIB_7322_RcvCtrl_0_RcvIBPortEnable_RMASK 0x1
1785 #define QIB_7322_RcvCtrl_0_ContextEnableKernel_RMASK 0x1
1918 #define QIB_7322_RcvStatus_0_DmaeqBlockingContext_LSB 0x1
1923 #define QIB_7322_RcvStatus_0_RxPktInProgress_RMASK 0x1
1965 #define QIB_7322_SendCtrl_0_IBVLArbiterEn_RMASK 0x1
1968 #define QIB_7322_SendCtrl_0_TxeDrainRmFifo_RMASK 0x1
1971 #define QIB_7322_SendCtrl_0_TxeDrainLaFifo_RMASK 0x1
1974 #define QIB_7322_SendCtrl_0_SDmaHalt_RMASK 0x1
1977 #define QIB_7322_SendCtrl_0_SDmaEnable_RMASK 0x1
1980 #define QIB_7322_SendCtrl_0_SDmaSingleDescriptor_RMASK 0x1
1983 #define QIB_7322_SendCtrl_0_SDmaIntEnable_RMASK 0x1
1986 #define QIB_7322_SendCtrl_0_SDmaCleanup_RMASK 0x1
1989 #define QIB_7322_SendCtrl_0_ForceCreditUpToDate_RMASK 0x1
1992 #define QIB_7322_SendCtrl_0_SendEnable_RMASK 0x1
1993 #define QIB_7322_SendCtrl_0_TxeBypassIbc_LSB 0x1
1994 #define QIB_7322_SendCtrl_0_TxeBypassIbc_MSB 0x1
1995 #define QIB_7322_SendCtrl_0_TxeBypassIbc_RMASK 0x1
1998 #define QIB_7322_SendCtrl_0_TxeAbortIbc_RMASK 0x1
2046 #define QIB_7322_SendDmaStatus_0_ScoreBoardDrainInProg_RMASK 0x1
2049 #define QIB_7322_SendDmaStatus_0_HaltInProg_RMASK 0x1
2052 #define QIB_7322_SendDmaStatus_0_InternalSDmaHalt_RMASK 0x1
2064 #define QIB_7322_SendDmaStatus_0_ScbFull_RMASK 0x1
2067 #define QIB_7322_SendDmaStatus_0_ScbEmpty_RMASK 0x1
2070 #define QIB_7322_SendDmaStatus_0_ScbEntryValid_RMASK 0x1
2073 #define QIB_7322_SendDmaStatus_0_ScbFetchDescFlag_RMASK 0x1
2076 #define QIB_7322_SendDmaStatus_0_SplFifoReadyToGo_RMASK 0x1
2079 #define QIB_7322_SendDmaStatus_0_SplFifoDisarmed_RMASK 0x1
2082 #define QIB_7322_SendDmaStatus_0_SplFifoEmpty_RMASK 0x1
2085 #define QIB_7322_SendDmaStatus_0_SplFifoFull_RMASK 0x1
2103 #define QIB_7322_SendHdrErrSymptom_0_NonKeyPacket_RMASK 0x1
2106 #define QIB_7322_SendHdrErrSymptom_0_GRHFail_RMASK 0x1
2109 #define QIB_7322_SendHdrErrSymptom_0_PkeyFail_RMASK 0x1
2112 #define QIB_7322_SendHdrErrSymptom_0_QPFail_RMASK 0x1
2115 #define QIB_7322_SendHdrErrSymptom_0_SLIDFail_RMASK 0x1
2116 #define QIB_7322_SendHdrErrSymptom_0_RawIPV6_LSB 0x1
2117 #define QIB_7322_SendHdrErrSymptom_0_RawIPV6_MSB 0x1
2118 #define QIB_7322_SendHdrErrSymptom_0_RawIPV6_RMASK 0x1
2121 #define QIB_7322_SendHdrErrSymptom_0_PacketTooSmall_RMASK 0x1
2142 #define QIB_7322_SendCheckControl_0_PKey_En_RMASK 0x1
2145 #define QIB_7322_SendCheckControl_0_BTHQP_En_RMASK 0x1
2148 #define QIB_7322_SendCheckControl_0_SLID_En_RMASK 0x1
2149 #define QIB_7322_SendCheckControl_0_RawIPV6_En_LSB 0x1
2150 #define QIB_7322_SendCheckControl_0_RawIPV6_En_MSB 0x1
2151 #define QIB_7322_SendCheckControl_0_RawIPV6_En_RMASK 0x1
2154 #define QIB_7322_SendCheckControl_0_PacketTooSmall_En_RMASK 0x1
2172 #define QIB_7322_IBCStatusA_0_TxCreditOk_VL7_RMASK 0x1
2175 #define QIB_7322_IBCStatusA_0_TxCreditOk_VL6_RMASK 0x1
2178 #define QIB_7322_IBCStatusA_0_TxCreditOk_VL5_RMASK 0x1
2181 #define QIB_7322_IBCStatusA_0_TxCreditOk_VL4_RMASK 0x1
2184 #define QIB_7322_IBCStatusA_0_TxCreditOk_VL3_RMASK 0x1
2187 #define QIB_7322_IBCStatusA_0_TxCreditOk_VL2_RMASK 0x1
2190 #define QIB_7322_IBCStatusA_0_TxCreditOk_VL1_RMASK 0x1
2193 #define QIB_7322_IBCStatusA_0_TxCreditOk_VL0_RMASK 0x1
2196 #define QIB_7322_IBCStatusA_0_TxReady_RMASK 0x1
2199 #define QIB_7322_IBCStatusA_0_LinkSpeedQDR_RMASK 0x1
2202 #define QIB_7322_IBCStatusA_0_ScrambleCapRemote_RMASK 0x1
2205 #define QIB_7322_IBCStatusA_0_ScrambleEn_RMASK 0x1
2208 #define QIB_7322_IBCStatusA_0_IBTxLaneReversed_RMASK 0x1
2211 #define QIB_7322_IBCStatusA_0_IBRxLaneReversed_RMASK 0x1
2214 #define QIB_7322_IBCStatusA_0_DDS_RXEQ_FAIL_RMASK 0x1
2217 #define QIB_7322_IBCStatusA_0_LinkWidthActive_RMASK 0x1
2220 #define QIB_7322_IBCStatusA_0_LinkSpeedActive_RMASK 0x1
2232 #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_debug_RMASK 0x1
2235 #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_reached_threshold_RMASK 0x1
2238 #define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_started_RMASK 0x1
2241 #define QIB_7322_IBCStatusB_0_heartbeat_timed_out_RMASK 0x1
2259 #define QIB_7322_IBCCtrlA_0_Loopback_RMASK 0x1
2262 #define QIB_7322_IBCCtrlA_0_LinkDownDefaultState_RMASK 0x1
2265 #define QIB_7322_IBCCtrlA_0_IBLinkEn_RMASK 0x1
2268 #define QIB_7322_IBCCtrlA_0_IBStatIntReductionEn_RMASK 0x1
2304 #define QIB_7322_IBCCtrlB_0_IB_ENABLE_FILT_DPKT_RMASK 0x1
2307 #define QIB_7322_IBCCtrlB_0_HRTBT_REQ_RMASK 0x1
2313 #define QIB_7322_IBCCtrlB_0_HRTBT_AUTO_RMASK 0x1
2316 #define QIB_7322_IBCCtrlB_0_HRTBT_ENB_RMASK 0x1
2322 #define QIB_7322_IBCCtrlB_0_SD_DDSV_RMASK 0x1
2325 #define QIB_7322_IBCCtrlB_0_SD_ADD_ENB_RMASK 0x1
2328 #define QIB_7322_IBCCtrlB_0_SD_RX_EQUAL_ENABLE_RMASK 0x1
2331 #define QIB_7322_IBCCtrlB_0_IB_LANE_REV_SUPPORTED_RMASK 0x1
2334 #define QIB_7322_IBCCtrlB_0_IB_POLARITY_REV_SUPP_RMASK 0x1
2340 #define QIB_7322_IBCCtrlB_0_SD_SPEED_QDR_RMASK 0x1
2343 #define QIB_7322_IBCCtrlB_0_SD_SPEED_DDR_RMASK 0x1
2346 #define QIB_7322_IBCCtrlB_0_SD_SPEED_SDR_RMASK 0x1
2347 #define QIB_7322_IBCCtrlB_0_SD_SPEED_LSB 0x1
2348 #define QIB_7322_IBCCtrlB_0_SD_SPEED_MSB 0x1
2349 #define QIB_7322_IBCCtrlB_0_SD_SPEED_RMASK 0x1
2352 #define QIB_7322_IBCCtrlB_0_IB_ENHANCED_MODE_RMASK 0x1
2382 #define QIB_7322_IB_SDTEST_IF_TX_0_CREDIT_CHANGE_RMASK 0x1
2386 #define QIB_7322_IB_SDTEST_IF_TX_0_TS_3_TX_VALID_LSB 0x1
2387 #define QIB_7322_IB_SDTEST_IF_TX_0_TS_3_TX_VALID_MSB 0x1
2388 #define QIB_7322_IB_SDTEST_IF_TX_0_TS_3_TX_VALID_RMASK 0x1
2391 #define QIB_7322_IB_SDTEST_IF_TX_0_TS_T_TX_VALID_RMASK 0x1
2407 #define QIB_7322_IB_SDTEST_IF_RX_0_TS_3_RX_VALID_LSB 0x1
2408 #define QIB_7322_IB_SDTEST_IF_RX_0_TS_3_RX_VALID_MSB 0x1
2409 #define QIB_7322_IB_SDTEST_IF_RX_0_TS_3_RX_VALID_RMASK 0x1
2412 #define QIB_7322_IB_SDTEST_IF_RX_0_TS_T_RX_VALID_RMASK 0x1
2418 #define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteForce_RMASK 0x1
2421 #define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteMask_RMASK 0x1
2424 #define QIB_7322_IBNCModeCtrl_0_ScrambleCapLocal_RMASK 0x1
2433 #define QIB_7322_IBNCModeCtrl_0_TSMEnable_ignore_TSM_on_rx_RMASK 0x1
2434 #define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS2_LSB 0x1
2435 #define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS2_MSB 0x1
2436 #define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS2_RMASK 0x1
2439 #define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS1_RMASK 0x1
2451 #define QIB_7322_IBPCSConfig_0_xcv_rreset_RMASK 0x1
2452 #define QIB_7322_IBPCSConfig_0_xcv_treset_LSB 0x1
2453 #define QIB_7322_IBPCSConfig_0_xcv_treset_MSB 0x1
2454 #define QIB_7322_IBPCSConfig_0_xcv_treset_RMASK 0x1
2457 #define QIB_7322_IBPCSConfig_0_tx_rx_reset_RMASK 0x1
2463 #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_QDR_RMASK 0x1
2466 #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_DDR_RMASK 0x1
2469 #define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_SDR_RMASK 0x1
2478 #define QIB_7322_IBSerdesCtrl_0_IB_LAT_MODE_RMASK 0x1
2481 #define QIB_7322_IBSerdesCtrl_0_RXLOSEN_RMASK 0x1
2484 #define QIB_7322_IBSerdesCtrl_0_LPEN_RMASK 0x1
2487 #define QIB_7322_IBSerdesCtrl_0_PLLPD_RMASK 0x1
2490 #define QIB_7322_IBSerdesCtrl_0_TXPD_RMASK 0x1
2493 #define QIB_7322_IBSerdesCtrl_0_RXPD_RMASK 0x1
2496 #define QIB_7322_IBSerdesCtrl_0_TXIDLE_RMASK 0x1
2505 #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_tx_override_deemphasis_select_RMASK 0x1
2508 #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_reset_tx_deemphasis_override_RMASK 0x1
2529 #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch3_RMASK 0x1
2532 #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch2_RMASK 0x1
2535 #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch1_RMASK 0x1
2538 #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch0_RMASK 0x1
2541 #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch3_RMASK 0x1
2544 #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch2_RMASK 0x1
2547 #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch1_RMASK 0x1
2550 #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch0_RMASK 0x1
2568 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch3_RMASK 0x1
2571 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch2_RMASK 0x1
2574 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch1_RMASK 0x1
2577 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch0_RMASK 0x1
2580 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch3_RMASK 0x1
2583 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch2_RMASK 0x1
2586 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch1_RMASK 0x1
2589 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch0_RMASK 0x1
2607 #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch3_RMASK 0x1
2610 #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch2_RMASK 0x1
2613 #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch1_RMASK 0x1
2616 #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch0_RMASK 0x1
2619 #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch3_RMASK 0x1
2622 #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch2_RMASK 0x1
2625 #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch1_RMASK 0x1
2628 #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch0_RMASK 0x1
2646 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch3_RMASK 0x1
2649 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch2_RMASK 0x1
2652 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch1_RMASK 0x1
2655 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch0_RMASK 0x1
2658 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch3_RMASK 0x1
2661 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch2_RMASK 0x1
2664 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch1_RMASK 0x1
2667 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch0_RMASK 0x1
2685 #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch3_RMASK 0x1
2688 #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch2_RMASK 0x1
2691 #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch1_RMASK 0x1
2694 #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch0_RMASK 0x1
2697 #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch3_RMASK 0x1
2700 #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch2_RMASK 0x1
2703 #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch1_RMASK 0x1
2706 #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch0_RMASK 0x1
2724 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch3_RMASK 0x1
2727 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch2_RMASK 0x1
2730 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch1_RMASK 0x1
2733 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch0_RMASK 0x1
2736 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch3_RMASK 0x1
2739 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch2_RMASK 0x1
2742 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch1_RMASK 0x1
2745 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch0_RMASK 0x1
3142 #define QIB_7322_RcvTIDFlowTable0_GenMismatch_RMASK 0x1
3145 #define QIB_7322_RcvTIDFlowTable0_SeqMismatch_RMASK 0x1
3148 #define QIB_7322_RcvTIDFlowTable0_KeepOnGenErr_RMASK 0x1
3151 #define QIB_7322_RcvTIDFlowTable0_KeepAfterSeqErr_RMASK 0x1
3154 #define QIB_7322_RcvTIDFlowTable0_HdrSuppEnabled_RMASK 0x1
3157 #define QIB_7322_RcvTIDFlowTable0_FlowValid_RMASK 0x1