Lines Matching full:x1
50 #define RDMA_CQE_RESPONDER_TOGGLE_BIT_MASK 0x1
54 #define RDMA_CQE_RESPONDER_INV_FLG_MASK 0x1
56 #define RDMA_CQE_RESPONDER_IMM_FLG_MASK 0x1
58 #define RDMA_CQE_RESPONDER_RDMA_FLG_MASK 0x1
74 #define RDMA_CQE_REQUESTER_TOGGLE_BIT_MASK 0x1
88 #define RDMA_CQE_COMMON_TOGGLE_BIT_MASK 0x1
206 #define RDMA_PWM_VAL32_DATA_BYPASS_EN_MASK 0x1
208 #define RDMA_PWM_VAL32_DATA_CONN_TYPE_IS_IWARP_MASK 0x1
210 #define RDMA_PWM_VAL32_DATA_SET_16B_VAL_MASK 0x1
236 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_CRC_MASK 0x1
238 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_APP_TAG_MASK 0x1
240 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_REF_TAG_MASK 0x1
244 #define RDMA_DIF_ERROR_RESULT_TOGGLE_BIT_MASK 0x1
262 #define RDMA_DIF_PARAMS_IO_DIRECTION_FLG_MASK 0x1
264 #define RDMA_DIF_PARAMS_BLOCK_SIZE_MASK 0x1
266 #define RDMA_DIF_PARAMS_RUNT_VALID_FLG_MASK 0x1
268 #define RDMA_DIF_PARAMS_VALIDATE_CRC_GUARD_MASK 0x1
270 #define RDMA_DIF_PARAMS_VALIDATE_REF_TAG_MASK 0x1
272 #define RDMA_DIF_PARAMS_VALIDATE_APP_TAG_MASK 0x1
274 #define RDMA_DIF_PARAMS_CRC_SEED_MASK 0x1
276 #define RDMA_DIF_PARAMS_RX_REF_TAG_CONST_MASK 0x1
278 #define RDMA_DIF_PARAMS_BLOCK_GUARD_TYPE_MASK 0x1
280 #define RDMA_DIF_PARAMS_APP_ESCAPE_MASK 0x1
282 #define RDMA_DIF_PARAMS_REF_ESCAPE_MASK 0x1
296 #define RDMA_SQ_ATOMIC_WQE_COMP_FLG_MASK 0x1
298 #define RDMA_SQ_ATOMIC_WQE_RD_FENCE_FLG_MASK 0x1
300 #define RDMA_SQ_ATOMIC_WQE_INV_FENCE_FLG_MASK 0x1
302 #define RDMA_SQ_ATOMIC_WQE_SE_FLG_MASK 0x1
304 #define RDMA_SQ_ATOMIC_WQE_INLINE_FLG_MASK 0x1
306 #define RDMA_SQ_ATOMIC_WQE_DIF_ON_HOST_FLG_MASK 0x1
326 #define RDMA_SQ_ATOMIC_WQE_1ST_COMP_FLG_MASK 0x1
328 #define RDMA_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_MASK 0x1
330 #define RDMA_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_MASK 0x1
332 #define RDMA_SQ_ATOMIC_WQE_1ST_SE_FLG_MASK 0x1
334 #define RDMA_SQ_ATOMIC_WQE_1ST_INLINE_FLG_MASK 0x1
360 #define RDMA_SQ_BIND_WQE_COMP_FLG_MASK 0x1
362 #define RDMA_SQ_BIND_WQE_RD_FENCE_FLG_MASK 0x1
364 #define RDMA_SQ_BIND_WQE_INV_FENCE_FLG_MASK 0x1
366 #define RDMA_SQ_BIND_WQE_SE_FLG_MASK 0x1
368 #define RDMA_SQ_BIND_WQE_INLINE_FLG_MASK 0x1
370 #define RDMA_SQ_BIND_WQE_DIF_ON_HOST_FLG_MASK 0x1
377 #define RDMA_SQ_BIND_WQE_ZERO_BASED_MASK 0x1
382 #define RDMA_SQ_BIND_WQE_REMOTE_READ_MASK 0x1
384 #define RDMA_SQ_BIND_WQE_REMOTE_WRITE_MASK 0x1
386 #define RDMA_SQ_BIND_WQE_ENABLE_ATOMIC_MASK 0x1
388 #define RDMA_SQ_BIND_WQE_LOCAL_READ_MASK 0x1
390 #define RDMA_SQ_BIND_WQE_LOCAL_WRITE_MASK 0x1
408 #define RDMA_SQ_BIND_WQE_1ST_COMP_FLG_MASK 0x1
410 #define RDMA_SQ_BIND_WQE_1ST_RD_FENCE_FLG_MASK 0x1
412 #define RDMA_SQ_BIND_WQE_1ST_INV_FENCE_FLG_MASK 0x1
414 #define RDMA_SQ_BIND_WQE_1ST_SE_FLG_MASK 0x1
416 #define RDMA_SQ_BIND_WQE_1ST_INLINE_FLG_MASK 0x1
427 #define RDMA_SQ_BIND_WQE_2ND_ZERO_BASED_MASK 0x1
432 #define RDMA_SQ_BIND_WQE_2ND_REMOTE_READ_MASK 0x1
434 #define RDMA_SQ_BIND_WQE_2ND_REMOTE_WRITE_MASK 0x1
436 #define RDMA_SQ_BIND_WQE_2ND_ENABLE_ATOMIC_MASK 0x1
438 #define RDMA_SQ_BIND_WQE_2ND_LOCAL_READ_MASK 0x1
440 #define RDMA_SQ_BIND_WQE_2ND_LOCAL_WRITE_MASK 0x1
463 #define RDMA_SQ_COMMON_WQE_COMP_FLG_MASK 0x1
465 #define RDMA_SQ_COMMON_WQE_RD_FENCE_FLG_MASK 0x1
467 #define RDMA_SQ_COMMON_WQE_INV_FENCE_FLG_MASK 0x1
469 #define RDMA_SQ_COMMON_WQE_SE_FLG_MASK 0x1
471 #define RDMA_SQ_COMMON_WQE_INLINE_FLG_MASK 0x1
484 #define RDMA_SQ_FMR_WQE_COMP_FLG_MASK 0x1
486 #define RDMA_SQ_FMR_WQE_RD_FENCE_FLG_MASK 0x1
488 #define RDMA_SQ_FMR_WQE_INV_FENCE_FLG_MASK 0x1
490 #define RDMA_SQ_FMR_WQE_SE_FLG_MASK 0x1
492 #define RDMA_SQ_FMR_WQE_INLINE_FLG_MASK 0x1
494 #define RDMA_SQ_FMR_WQE_DIF_ON_HOST_FLG_MASK 0x1
503 #define RDMA_SQ_FMR_WQE_ZERO_BASED_MASK 0x1
505 #define RDMA_SQ_FMR_WQE_BIND_EN_MASK 0x1
507 #define RDMA_SQ_FMR_WQE_RESERVED1_MASK 0x1
510 #define RDMA_SQ_FMR_WQE_REMOTE_READ_MASK 0x1
512 #define RDMA_SQ_FMR_WQE_REMOTE_WRITE_MASK 0x1
514 #define RDMA_SQ_FMR_WQE_ENABLE_ATOMIC_MASK 0x1
516 #define RDMA_SQ_FMR_WQE_LOCAL_READ_MASK 0x1
518 #define RDMA_SQ_FMR_WQE_LOCAL_WRITE_MASK 0x1
534 #define RDMA_SQ_FMR_WQE_1ST_COMP_FLG_MASK 0x1
536 #define RDMA_SQ_FMR_WQE_1ST_RD_FENCE_FLG_MASK 0x1
538 #define RDMA_SQ_FMR_WQE_1ST_INV_FENCE_FLG_MASK 0x1
540 #define RDMA_SQ_FMR_WQE_1ST_SE_FLG_MASK 0x1
542 #define RDMA_SQ_FMR_WQE_1ST_INLINE_FLG_MASK 0x1
544 #define RDMA_SQ_FMR_WQE_1ST_DIF_ON_HOST_FLG_MASK 0x1
557 #define RDMA_SQ_FMR_WQE_2ND_ZERO_BASED_MASK 0x1
559 #define RDMA_SQ_FMR_WQE_2ND_BIND_EN_MASK 0x1
561 #define RDMA_SQ_FMR_WQE_2ND_RESERVED1_MASK 0x1
564 #define RDMA_SQ_FMR_WQE_2ND_REMOTE_READ_MASK 0x1
566 #define RDMA_SQ_FMR_WQE_2ND_REMOTE_WRITE_MASK 0x1
568 #define RDMA_SQ_FMR_WQE_2ND_ENABLE_ATOMIC_MASK 0x1
570 #define RDMA_SQ_FMR_WQE_2ND_LOCAL_READ_MASK 0x1
572 #define RDMA_SQ_FMR_WQE_2ND_LOCAL_WRITE_MASK 0x1
588 #define RDMA_SQ_LOCAL_INV_WQE_COMP_FLG_MASK 0x1
590 #define RDMA_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_MASK 0x1
592 #define RDMA_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_MASK 0x1
594 #define RDMA_SQ_LOCAL_INV_WQE_SE_FLG_MASK 0x1
596 #define RDMA_SQ_LOCAL_INV_WQE_INLINE_FLG_MASK 0x1
598 #define RDMA_SQ_LOCAL_INV_WQE_DIF_ON_HOST_FLG_MASK 0x1
612 #define RDMA_SQ_RDMA_WQE_COMP_FLG_MASK 0x1
614 #define RDMA_SQ_RDMA_WQE_RD_FENCE_FLG_MASK 0x1
616 #define RDMA_SQ_RDMA_WQE_INV_FENCE_FLG_MASK 0x1
618 #define RDMA_SQ_RDMA_WQE_SE_FLG_MASK 0x1
620 #define RDMA_SQ_RDMA_WQE_INLINE_FLG_MASK 0x1
622 #define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_MASK 0x1
624 #define RDMA_SQ_RDMA_WQE_READ_INV_FLG_MASK 0x1
626 #define RDMA_SQ_RDMA_WQE_RESERVED1_MASK 0x1
633 #define RDMA_SQ_RDMA_WQE_DIF_BLOCK_SIZE_MASK 0x1
647 #define RDMA_SQ_RDMA_WQE_1ST_COMP_FLG_MASK 0x1
649 #define RDMA_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_MASK 0x1
651 #define RDMA_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_MASK 0x1
653 #define RDMA_SQ_RDMA_WQE_1ST_SE_FLG_MASK 0x1
655 #define RDMA_SQ_RDMA_WQE_1ST_INLINE_FLG_MASK 0x1
657 #define RDMA_SQ_RDMA_WQE_1ST_DIF_ON_HOST_FLG_MASK 0x1
659 #define RDMA_SQ_RDMA_WQE_1ST_READ_INV_FLG_MASK 0x1
661 #define RDMA_SQ_RDMA_WQE_1ST_RESERVED0_MASK 0x1
672 #define RDMA_SQ_RDMA_WQE_2ND_DIF_BLOCK_SIZE_MASK 0x1
674 #define RDMA_SQ_RDMA_WQE_2ND_DIF_FIRST_SEGMENT_FLG_MASK 0x1
676 #define RDMA_SQ_RDMA_WQE_2ND_DIF_LAST_SEGMENT_FLG_MASK 0x1
706 #define RDMA_SQ_SEND_WQE_COMP_FLG_MASK 0x1
708 #define RDMA_SQ_SEND_WQE_RD_FENCE_FLG_MASK 0x1
710 #define RDMA_SQ_SEND_WQE_INV_FENCE_FLG_MASK 0x1
712 #define RDMA_SQ_SEND_WQE_SE_FLG_MASK 0x1
714 #define RDMA_SQ_SEND_WQE_INLINE_FLG_MASK 0x1
716 #define RDMA_SQ_SEND_WQE_DIF_ON_HOST_FLG_MASK 0x1
731 #define RDMA_SQ_SEND_WQE_1ST_COMP_FLG_MASK 0x1
733 #define RDMA_SQ_SEND_WQE_1ST_RD_FENCE_FLG_MASK 0x1
735 #define RDMA_SQ_SEND_WQE_1ST_INV_FENCE_FLG_MASK 0x1
737 #define RDMA_SQ_SEND_WQE_1ST_SE_FLG_MASK 0x1
739 #define RDMA_SQ_SEND_WQE_1ST_INLINE_FLG_MASK 0x1