1935 	context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);  in handle_eth_ud_smac_index()
1942 			context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;  in handle_eth_ud_smac_index()
2093 			pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;  in fill_qp_rss_context()
2242 			mlx4_set_sched(&context->pri_path, attr->port_num);  in __mlx4_ib_modify_qp()
2258 			context->pri_path.counter_index = counter_index;  in __mlx4_ib_modify_qp()
2261 				context->pri_path.fl |=  in __mlx4_ib_modify_qp()
2263 				context->pri_path.vlan_control |=  in __mlx4_ib_modify_qp()
2267 			context->pri_path.counter_index =  in __mlx4_ib_modify_qp()
2286 			context->pri_path.disable_pkey_check = 0x40;  in __mlx4_ib_modify_qp()
2287 		context->pri_path.pkey_index = attr->pkey_index;  in __mlx4_ib_modify_qp()
2308 		if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,  in __mlx4_ib_modify_qp()
2329 		context->pri_path.ackto |= attr->timeout << 3;  in __mlx4_ib_modify_qp()
2444 		context->pri_path.sched_queue = (qp->port - 1) << 6;  in __mlx4_ib_modify_qp()
2448 			context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;  in __mlx4_ib_modify_qp()
2450 				context->pri_path.fl = 0x80;  in __mlx4_ib_modify_qp()
2453 				context->pri_path.fl = 0x80;  in __mlx4_ib_modify_qp()
2454 			context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;  in __mlx4_ib_modify_qp()
2460 				context->pri_path.feup = 1 << 7; /* don't fsm */  in __mlx4_ib_modify_qp()
2477 		context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |  in __mlx4_ib_modify_qp()
2491 			context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;  in __mlx4_ib_modify_qp()
4052 		to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);  in mlx4_ib_query_qp()
4059 	qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;  in mlx4_ib_query_qp()
4063 		qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;  in mlx4_ib_query_qp()
4074 	qp_attr->timeout	    = context.pri_path.ackto >> 3;  in mlx4_ib_query_qp()