Lines Matching refs:GENMASK_ULL

19 #define IRDMA_UDA_QPSQ_INLINEDATALEN GENMASK_ULL(55, 48)
20 #define IRDMA_UDA_QPSQ_ADDFRAGCNT GENMASK_ULL(41, 38)
21 #define IRDMA_UDA_QPSQ_IPFRAGFLAGS GENMASK_ULL(43, 42)
25 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
26 #define IRDMA_UDA_QPSQ_PROTOCOL GENMASK_ULL(23, 16)
27 #define IRDMA_UDA_QPSQ_EXTHDRLEN GENMASK_ULL(40, 32)
29 #define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56)
31 #define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)
33 #define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30)
35 #define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28)
41 #define IRDMA_UDA_QPSQ_IMMDATA GENMASK_ULL(63, 0)
49 #define IRDMA_UDAQPC_PDINDEXHI GENMASK_ULL(21, 20)
69 #define IRDMA_UDAQPC_RQHDRRINGBUFSIZE GENMASK_ULL(49, 48)
70 #define IRDMA_UDAQPC_SQHDRRINGBUFSIZE GENMASK_ULL(33, 32)
73 #define IRDMA_UDAQPC_STATISTICS_INSTANCE_INDEX GENMASK_ULL(6, 0)
78 #define IRDMA_UDAQPC_IPID GENMASK_ULL(47, 32)
79 #define IRDMA_UDAQPC_SNDMSS GENMASK_ULL(29, 16)
80 #define IRDMA_UDAQPC_VLANTAG GENMASK_ULL(15, 0)
82 #define IRDMA_UDA_CQPSQ_MAV_PDINDEXHI GENMASK_ULL(21, 20)
83 #define IRDMA_UDA_CQPSQ_MAV_PDINDEXLO GENMASK_ULL(63, 48)
84 #define IRDMA_UDA_CQPSQ_MAV_SRCMACADDRINDEX GENMASK_ULL(29, 24)
85 #define IRDMA_UDA_CQPSQ_MAV_ARPINDEX GENMASK_ULL(63, 48)
86 #define IRDMA_UDA_CQPSQ_MAV_TC GENMASK_ULL(39, 32)
87 #define IRDMA_UDA_CQPSQ_MAV_HOPLIMIT GENMASK_ULL(39, 32)
88 #define IRDMA_UDA_CQPSQ_MAV_FLOWLABEL GENMASK_ULL(19, 0)
89 #define IRDMA_UDA_CQPSQ_MAV_ADDR0 GENMASK_ULL(63, 32)
90 #define IRDMA_UDA_CQPSQ_MAV_ADDR1 GENMASK_ULL(31, 0)
91 #define IRDMA_UDA_CQPSQ_MAV_ADDR2 GENMASK_ULL(63, 32)
92 #define IRDMA_UDA_CQPSQ_MAV_ADDR3 GENMASK_ULL(31, 0)
94 #define IRDMA_UDA_CQPSQ_MAV_OPCODE GENMASK_ULL(37, 32)
97 #define IRDMA_UDA_CQPSQ_MAV_AVIDX GENMASK_ULL(16, 0)
100 #define IRDMA_UDA_MGCTX_DESTPORT GENMASK_ULL(47, 32)
101 #define IRDMA_UDA_MGCTX_VFID GENMASK_ULL(28, 22)
103 #define IRDMA_UDA_MGCTX_PFID GENMASK_ULL(21, 18)
105 #define IRDMA_UDA_MGCTX_QPID GENMASK_ULL(17, 0)
107 #define IRDMA_UDA_CQPSQ_MG_OPCODE GENMASK_ULL(37, 32)
108 #define IRDMA_UDA_CQPSQ_MG_MGIDX GENMASK_ULL(12, 0)
111 #define IRDMA_UDA_CQPSQ_MG_HMC_FCN_ID GENMASK_ULL(5, 0)
112 #define IRDMA_UDA_CQPSQ_MG_VLANID GENMASK_ULL(43, 32)
113 #define IRDMA_UDA_CQPSQ_QS_HANDLE GENMASK_ULL(9, 0)
114 #define IRDMA_UDA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)
116 #define IRDMA_UDA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16)
117 #define IRDMA_UDA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)
118 #define IRDMA_UDA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
119 #define IRDMA_UDA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)
120 #define IRDMA_UDA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
121 #define IRDMA_UDA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)
123 #define IRDMA_UDA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)
124 #define IRDMA_UDA_CQPSQ_QHASH_MANAGE GENMASK_ULL(62, 61)
125 #define IRDMA_UDA_CQPSQ_QHASH_IPV4VALID GENMASK_ULL(60, 60)
126 #define IRDMA_UDA_CQPSQ_QHASH_LANFWD GENMASK_ULL(59, 59)
127 #define IRDMA_UDA_CQPSQ_QHASH_ENTRYTYPE GENMASK_ULL(44, 42)