Lines Matching +full:32 +full:- +full:63
1 /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
123 ((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
141 #define IRDMA_QP_WQE_MIN_SIZE 32
198 IRDMA_OP_MC_DESTROY = 32,
359 (((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
361 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
363 (((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
365 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
374 #define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)
375 #define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)
379 #define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
381 #define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
383 #define IRDMA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)
384 #define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)
389 #define IRDMA_CQPSQ_STATS_WQEVALID BIT_ULL(63)
393 #define IRDMA_CQPSQ_STATS_OP GENMASK_ULL(37, 32)
396 #define IRDMA_CQPSQ_WS_WQEVALID BIT_ULL(63)
405 #define IRDMA_CQPSQ_WS_OP GENMASK_ULL(37, 32)
409 #define IRDMA_CQPSQ_WS_WEIGHT GENMASK_ULL(38, 32)
411 #define IRDMA_CQPSQ_UP_WQEVALID BIT_ULL(63)
414 #define IRDMA_CQPSQ_UP_OP GENMASK_ULL(37, 32)
416 #define IRDMA_CQPSQ_UP_CNPOVERRIDE GENMASK_ULL(37, 32)
417 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID BIT_ULL(63)
419 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP GENMASK_ULL(37, 32)
420 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED GENMASK_ULL(47, 32)
430 #define IRDMA_CQPHC_HAI_FACTOR GENMASK_ULL(47, 32)
431 #define IRDMA_CQPHC_RAI_FACTOR GENMASK_ULL(63, 48)
435 #define IRDMA_CQPHC_RREDUCE_MPERIOD GENMASK_ULL(63, 32)
442 #define IRDMA_CQPHC_CEQPERVF GENMASK_ULL(39, 32)
444 #define IRDMA_CQPHC_ENABLED_VFS GENMASK_ULL(37, 32)
448 #define IRDMA_CQPHC_SQBASE GENMASK_ULL(63, 9)
450 #define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0)
465 #define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32)
471 #define IRDMA_CQ_VALID BIT_ULL(63)
476 #define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48)
481 #define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32)
483 #define IRDMACQ_TCPSEQNUMRTT GENMASK_ULL(63, 32)
485 #define IRDMACQ_QPID GENMASK_ULL(55, 32)
495 #define IRDMA_CEQE_VALID BIT_ULL(63)
501 #define IRDMA_AEQE_WQDESCIDX GENMASK_ULL(32, 18)
508 #define IRDMA_AEQE_VALID BIT_ULL(63)
511 #define IRDMA_UDA_QPSQ_OPCODE GENMASK_ULL(37, 32)
515 #define IRDMA_UDA_QPSQ_VALID BIT_ULL(63)
528 #define IRDMA_CQPSQ_OPCODE GENMASK_ULL(37, 32)
529 #define IRDMA_CQPSQ_WQEVALID BIT_ULL(63)
539 #define IRDMA_CQPSQ_QP_NEWMSS GENMASK_ULL(45, 32)
547 #define IRDMA_CQPSQ_QP_OP_S 32
572 #define IRDMA_CQPSQ_CQ_OP GENMASK_ULL(37, 32)
588 #define IRDMA_CQPSQ_STAG_PARENTSTAGIDX GENMASK_ULL(55, 32)
613 #define IRDMA_CQPSQ_MLM_MAC4 GENMASK_ULL(39, 32)
623 #define IRDMA_CQPSQ_MVPBP_SD_INX GENMASK_ULL(43, 32)
625 #define IRDMA_CQPSQ_MVPBP_PD_PLPBA GENMASK_ULL(63, 3)
627 /* Manage Push Page - MPP */
637 /* Upload Context - UCTX */
649 #define IRDMA_CQPSQ_SHMCRP_VFNUM GENMASK_ULL(37, 32)
664 #define IRDMA_COMMIT_FPM_BASE_S 32
670 #define IRDMA_CQPSQ_FWQE_SQMNERR GENMASK_ULL(47, 32)
671 #define IRDMA_CQPSQ_FWQE_SQMJERR GENMASK_ULL(63, 48)
681 #define IRDMA_CQPSQ_UPESD_SDDATAHI GENMASK_ULL(63, 32)
683 #define IRDMA_CQPSQ_UPESD_ENTRY_VALID BIT_ULL(63)
689 #define IRDMA_CQPSQ_UPESD_BM GENMASK_ULL(34, 32)
724 #define IRDMAQPC_PPIDX GENMASK_ULL(41, 32)
726 #define IRDMAQPC_RDMAP_VER GENMASK_ULL(63, 62)
727 #define IRDMAQPC_ROCE_TVER GENMASK_ULL(63, 60)
737 #define IRDMAQPC_SRCPORTNUM GENMASK_ULL(47, 32)
738 #define IRDMAQPC_DESTPORTNUM GENMASK_ULL(63, 48)
739 #define IRDMAQPC_DESTIPADDR0 GENMASK_ULL(63, 32)
741 #define IRDMAQPC_DESTIPADDR2 GENMASK_ULL(63, 32)
745 #define IRDMAQPC_VLANTAG GENMASK_ULL(47, 32)
746 #define IRDMAQPC_ARPIDX GENMASK_ULL(63, 48)
753 #define IRDMAQPC_RCVSCALE GENMASK_ULL(35, 32)
755 #define IRDMAQPC_PDIDX GENMASK_ULL(63, 48)
757 #define IRDMAQPC_PKEY GENMASK_ULL(47, 32)
759 #define IRDMAQPC_QKEY GENMASK_ULL(63, 32)
764 #define IRDMAQPC_TIMESTAMP_AGE GENMASK_ULL(63, 32)
766 #define IRDMAQPC_ISN GENMASK_ULL(55, 32)
768 #define IRDMAQPC_LSN GENMASK_ULL(55, 32)
769 #define IRDMAQPC_SNDWND GENMASK_ULL(63, 32)
772 #define IRDMAQPC_RCVWND GENMASK_ULL(63, 32)
774 #define IRDMAQPC_SNDUNA GENMASK_ULL(63, 32)
776 #define IRDMAQPC_PSNUNA GENMASK_ULL(55, 32)
778 #define IRDMAQPC_RTTVAR GENMASK_ULL(63, 32)
780 #define IRDMAQPC_CWND GENMASK_ULL(63, 32)
781 #define IRDMAQPC_CWNDROCE GENMASK_ULL(55, 32)
783 #define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32)
784 #define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(45, 32)
785 #define IRDMAQPC_RTOMIN GENMASK_ULL(63, 57)
790 #define IRDMAQPC_RXCQNUM GENMASK_ULL(50, 32)
792 #define IRDMAQPC_Q2ADDR GENMASK_ULL(63, 8)
794 #define IRDMAQPC_MACADDRESS GENMASK_ULL(63, 16)
810 #define IRDMAQPC_THIGH GENMASK_ULL(63, 52)
811 #define IRDMAQPC_TLOW GENMASK_ULL(39, 32)
818 #define IRDMAQPC_RCVMARKOFFSET GENMASK_ULL(40, 32)
825 #define IRDMAQPC_EXCEPTION_LAN_QUEUE GENMASK_ULL(43, 32)
827 #define IRDMAQPC_LOCAL_IPADDR2 GENMASK_ULL(63, 32)
829 #define IRDMAQPC_LOCAL_IPADDR0 GENMASK_ULL(63, 32)
833 #define IRDMA_FEATURE_CNT GENMASK_ULL(47, 32)
834 #define IRDMA_FEATURE_TYPE GENMASK_ULL(63, 48)
836 #define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32)
847 #define IRDMAQPSQ_VALID BIT_ULL(63)
850 #define IRDMAQPSQ_FRAG_VALID BIT_ULL(63)
851 #define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32)
854 #define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32)
857 #define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32)
866 #define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0)
876 #define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32)
889 #define IRDMAQPSQ_FIRSTPMPBLIDXLO GENMASK_ULL(63, 48)
891 #define IRDMAQPSQ_PBLADDR GENMASK_ULL(63, 12)
908 #define IRDMA_QUERY_FPM_MAX_PE_SDS GENMASK_ULL(45, 32)
910 #define IRDMA_QUERY_FPM_XFBLOCKSIZE GENMASK_ULL(63, 32)
911 #define IRDMA_QUERY_FPM_Q1BLOCKSIZE GENMASK_ULL(63, 32)
913 #define IRDMA_QUERY_FPM_TIMERBUCKET GENMASK_ULL(47, 32)
914 #define IRDMA_QUERY_FPM_RRFBLOCKSIZE GENMASK_ULL(63, 32)
915 #define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE GENMASK_ULL(63, 32)
916 #define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE GENMASK_ULL(63, 32)
921 (_aeq)->aeqe_base[IRDMA_RING_CURRENT_TAIL((_aeq)->aeq_ring)].buf \
926 (_ceq)->ceqe_base[IRDMA_RING_CURRENT_TAIL((_ceq)->ceq_ring)].buf \
931 (_ceq)->ceqe_base[_pos].buf \
943 (_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
948 ((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
969 (_retcode) = -ENOMEM; \
980 (_retcode) = -ENOMEM; \
991 (_retcode) = -ENOMEM; \
998 if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \
1002 (_retcode) = -ENOMEM; \
1022 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1)) \
1027 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2)) \
1032 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3)) \
1037 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257)) \
1042 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258)) \
1046 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259)) \
1055 (((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \
1060 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \
1065 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \
1075 IRDMA_WQE_SIZE_32 = 32,
1088 enum { IRDMA_Q_ALIGNMENT_M = (128 - 1),
1089 IRDMA_AEQ_ALIGNMENT_M = (256 - 1),
1090 IRDMA_Q2_ALIGNMENT_M = (256 - 1),
1091 IRDMA_CEQ_ALIGNMENT_M = (256 - 1),
1092 IRDMA_CQ0_ALIGNMENT_M = (256 - 1),
1093 IRDMA_HOST_CTX_ALIGNMENT_M = (4 - 1),
1094 IRDMA_SHADOWAREA_M = (128 - 1),
1095 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M = (4 - 1),
1096 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M = (4 - 1),
1115 * set_64bit_val - set 64 bit value to hw wqe
1126 * set_32bit_val - set 32 bit value to hw wqe
1137 * get_64bit_val - read 64 bit value from wqe
1148 * get_32bit_val - read 32 bit value from wqe
1151 * @val: return 32 bit value