42 		dd_dev_err(dd, "pci enable failed: error %d\n", -ret);  in hfi1_pcie_init()
48 		dd_dev_err(dd, "pci_request_regions fails: err %d\n", -ret);  in hfi1_pcie_init()
61 			dd_dev_err(dd, "Unable to set DMA mask: %d\n", ret);  in hfi1_pcie_init()
109 		dd_dev_err(dd, "chip PIO range does not match\n");  in hfi1_pcie_ddinit()
115 		dd_dev_err(dd, "UC mapping of kregbase1 failed\n");  in hfi1_pcie_ddinit()
123 		dd_dev_err(dd, "Cannot read chip CSRs\n");  in hfi1_pcie_ddinit()
135 		dd_dev_err(dd, "UC mapping of kregbase2 failed\n");  in hfi1_pcie_ddinit()
143 		dd_dev_err(dd, "WC mapping of send buffers failed\n");  in hfi1_pcie_ddinit()
157 		dd_dev_err(dd, "WC mapping of receive array failed\n");  in hfi1_pcie_ddinit()
227 		dd_dev_err(dd, "Unable to read from PCI config\n");  in update_lbus_info()
248 		dd_dev_err(dd, "Can't find PCI Express capability!\n");  in pcie_speeds()
257 		dd_dev_err(dd, "Unable to read from PCI config\n");  in pcie_speeds()
341 	dd_dev_err(dd, "Unable to write to PCI config\n");  in restore_pci_variables()
400 	dd_dev_err(dd, "Unable to read from PCI config\n");  in save_pci_variables()
746 			dd_dev_err(dd, "Unable to read from PCI config\n");  in load_eq_table()
754 				dd_dev_err(dd,  in load_eq_table()
756 				dd_dev_err(dd, "         prec   attn   post\n");  in load_eq_table()
758 			dd_dev_err(dd, "   p%02d:   %02x     %02x     %02x\n",  in load_eq_table()
761 			dd_dev_err(dd, "            %02x     %02x     %02x\n",  in load_eq_table()
809 		dd_dev_err(dd, "%s: no parent device\n", __func__);  in trigger_sbr()
816 			dd_dev_err(dd,  in trigger_sbr()
1011 		dd_dev_err(dd, "The PCIe link is not Gen3 capable\n");  in do_pcie_gen3_transition()
1019 		dd_dev_err(dd, "%s: unable to acquire SBus resource\n",  in do_pcie_gen3_transition()
1126 		dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n",  in do_pcie_gen3_transition()
1206 		dd_dev_err(dd, "Unable to read from PCI config\n");  in do_pcie_gen3_transition()
1222 			dd_dev_err(dd, "Unable to write to PCI config\n");  in do_pcie_gen3_transition()
1233 		dd_dev_err(dd, "Unable to read from PCI config\n");  in do_pcie_gen3_transition()
1246 		dd_dev_err(dd, "Unable to write to PCI config\n");  in do_pcie_gen3_transition()
1301 		dd_dev_err(dd, "%s: Could not restore PCI variables\n",  in do_pcie_gen3_transition()
1323 		dd_dev_err(dd, "SBR failed - unable to read from device\n");  in do_pcie_gen3_transition()
1338 		dd_dev_err(dd, "Unable to read from PCI config\n");  in do_pcie_gen3_transition()
1349 		dd_dev_err(dd,  in do_pcie_gen3_transition()
1360 		dd_dev_err(dd, "%s: gasket error %d\n", __func__, err);  in do_pcie_gen3_transition()
1374 		dd_dev_err(dd, "PCIe link speed or width did not match target%s\n",  in do_pcie_gen3_transition()
1395 		dd_dev_err(dd, "Proceeding at current speed PCIe speed\n");  in do_pcie_gen3_transition()