90  * @bclk:		bus clock common for all ADCs, depends on part used
108 	struct clk			*bclk;  member
216 	if (!priv->bclk) {  in stm32h7_adc_clk_sel()
263 	rate = clk_get_rate(priv->bclk);  in stm32h7_adc_clk_sel()
269 	duty = clk_get_scaled_duty_cycle(priv->bclk, 100);  in stm32h7_adc_clk_sel()
558 	ret = clk_prepare_enable(priv->bclk);  in stm32_adc_core_hw_start()
575 	clk_disable_unprepare(priv->bclk);  in stm32_adc_core_hw_start()
594 	clk_disable_unprepare(priv->bclk);  in stm32_adc_core_hw_stop()
748 	priv->bclk = devm_clk_get_optional(&pdev->dev, "bus");  in stm32_adc_probe()
749 	if (IS_ERR(priv->bclk))  in stm32_adc_probe()
750 		return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk),  in stm32_adc_probe()