Lines Matching refs:STMP_OFFSET_REG_CLR

157 		       adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_read_single()
158 	writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_read_single()
166 		       adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_read_single()
170 	       adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_read_single()
193 	       adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_read_single()
406 	       adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_handle_irq()
441 	const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;  in mxs_lradc_adc_configure_trigger()
497 		       adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_preenable()
499 	       adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_preenable()
511 	       adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_preenable()
512 	writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_preenable()
527 	       adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_postdisable()
530 	       adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_postdisable()
533 		       adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);  in mxs_lradc_adc_buffer_postdisable()