Lines Matching full:adc
3 * Freescale MXS LRADC ADC driver
134 struct mxs_lradc_adc *adc = iio_priv(iio_dev); in mxs_lradc_adc_read_single() local
135 struct mxs_lradc *lradc = adc->lradc; in mxs_lradc_adc_read_single()
148 reinit_completion(&adc->completion); in mxs_lradc_adc_read_single()
157 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
158 writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
161 if (test_bit(chan, &adc->is_divided)) in mxs_lradc_adc_read_single()
163 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()
166 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
170 adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
171 writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()
173 writel(0, adc->base + LRADC_CH(0)); in mxs_lradc_adc_read_single()
177 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()
178 writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()
181 ret = wait_for_completion_killable_timeout(&adc->completion, HZ); in mxs_lradc_adc_read_single()
188 *val = readl(adc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK; in mxs_lradc_adc_read_single()
193 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
221 struct mxs_lradc_adc *adc = iio_priv(iio_dev); in mxs_lradc_adc_read_raw() local
241 *val = adc->vref_mv[chan->channel]; in mxs_lradc_adc_read_raw()
243 test_bit(chan->channel, &adc->is_divided); in mxs_lradc_adc_read_raw()
249 * The calculated value from the ADC is in Kelvin, we in mxs_lradc_adc_read_raw()
273 struct mxs_lradc_adc *adc = iio_priv(iio_dev); in mxs_lradc_adc_write_raw() local
275 adc->scale_avail[chan->channel]; in mxs_lradc_adc_write_raw()
288 clear_bit(chan->channel, &adc->is_divided); in mxs_lradc_adc_write_raw()
293 set_bit(chan->channel, &adc->is_divided); in mxs_lradc_adc_write_raw()
320 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_show_scale_avail() local
325 for (i = 0; i < ARRAY_SIZE(adc->scale_avail[ch]); i++) in mxs_lradc_adc_show_scale_avail()
327 adc->scale_avail[ch][i].integer, in mxs_lradc_adc_show_scale_avail()
328 adc->scale_avail[ch][i].nano); in mxs_lradc_adc_show_scale_avail()
387 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_handle_irq() local
388 struct mxs_lradc *lradc = adc->lradc; in mxs_lradc_adc_handle_irq()
389 unsigned long reg = readl(adc->base + LRADC_CTRL1); in mxs_lradc_adc_handle_irq()
397 spin_lock_irqsave(&adc->lock, flags); in mxs_lradc_adc_handle_irq()
399 spin_unlock_irqrestore(&adc->lock, flags); in mxs_lradc_adc_handle_irq()
402 complete(&adc->completion); in mxs_lradc_adc_handle_irq()
406 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_handle_irq()
417 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_trigger_handler() local
423 adc->buffer[j] = readl(adc->base + LRADC_CH(j)); in mxs_lradc_adc_trigger_handler()
424 writel(chan_value, adc->base + LRADC_CH(j)); in mxs_lradc_adc_trigger_handler()
425 adc->buffer[j] &= LRADC_CH_VALUE_MASK; in mxs_lradc_adc_trigger_handler()
426 adc->buffer[j] /= LRADC_DELAY_TIMER_LOOP; in mxs_lradc_adc_trigger_handler()
430 iio_push_to_buffers_with_timestamp(iio, adc->buffer, pf->timestamp); in mxs_lradc_adc_trigger_handler()
440 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_configure_trigger() local
443 writel(LRADC_DELAY_KICK, adc->base + (LRADC_DELAY(0) + st)); in mxs_lradc_adc_configure_trigger()
456 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_trigger_init() local
463 trig->dev.parent = adc->dev; in mxs_lradc_adc_trigger_init()
471 adc->trig = trig; in mxs_lradc_adc_trigger_init()
478 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_trigger_remove() local
480 iio_trigger_unregister(adc->trig); in mxs_lradc_adc_trigger_remove()
485 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_buffer_preenable() local
486 struct mxs_lradc *lradc = adc->lradc; in mxs_lradc_adc_buffer_preenable()
497 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_preenable()
499 adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_preenable()
505 writel(chan_value, adc->base + LRADC_CH(ofs)); in mxs_lradc_adc_buffer_preenable()
511 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_preenable()
512 writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_preenable()
513 writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_buffer_preenable()
514 writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_buffer_preenable()
516 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET); in mxs_lradc_adc_buffer_preenable()
523 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_buffer_postdisable() local
524 struct mxs_lradc *lradc = adc->lradc; in mxs_lradc_adc_buffer_postdisable()
527 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_postdisable()
530 adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_postdisable()
533 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_buffer_postdisable()
541 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_validate_scan_mask() local
542 struct mxs_lradc *lradc = adc->lradc; in mxs_lradc_adc_validate_scan_mask()
665 static void mxs_lradc_adc_hw_init(struct mxs_lradc_adc *adc) in mxs_lradc_adc_hw_init() argument
667 /* The ADC always uses DELAY CHANNEL 0. */ in mxs_lradc_adc_hw_init()
672 /* Configure DELAY CHANNEL 0 for generic ADC sampling. */ in mxs_lradc_adc_hw_init()
673 writel(adc_cfg, adc->base + LRADC_DELAY(0)); in mxs_lradc_adc_hw_init()
680 writel(0, adc->base + LRADC_CTRL2); in mxs_lradc_adc_hw_init()
683 static void mxs_lradc_adc_hw_stop(struct mxs_lradc_adc *adc) in mxs_lradc_adc_hw_stop() argument
685 writel(0, adc->base + LRADC_DELAY(0)); in mxs_lradc_adc_hw_stop()
692 struct mxs_lradc_adc *adc; in mxs_lradc_adc_probe() local
700 iio = devm_iio_device_alloc(dev, sizeof(*adc)); in mxs_lradc_adc_probe()
706 adc = iio_priv(iio); in mxs_lradc_adc_probe()
707 adc->lradc = lradc; in mxs_lradc_adc_probe()
708 adc->dev = dev; in mxs_lradc_adc_probe()
714 adc->base = devm_ioremap(dev, iores->start, resource_size(iores)); in mxs_lradc_adc_probe()
715 if (!adc->base) in mxs_lradc_adc_probe()
718 init_completion(&adc->completion); in mxs_lradc_adc_probe()
719 spin_lock_init(&adc->lock); in mxs_lradc_adc_probe()
741 ret = stmp_reset_block(adc->base); in mxs_lradc_adc_probe()
768 adc->vref_mv = mxs_lradc_adc_vref_mv[lradc->soc]; in mxs_lradc_adc_probe()
770 /* Populate available ADC input ranges */ in mxs_lradc_adc_probe()
772 for (s = 0; s < ARRAY_SIZE(adc->scale_avail[i]); s++) { in mxs_lradc_adc_probe()
782 scale_uv = ((u64)adc->vref_mv[i] * 100000000) >> in mxs_lradc_adc_probe()
784 adc->scale_avail[i][s].nano = in mxs_lradc_adc_probe()
786 adc->scale_avail[i][s].integer = scale_uv; in mxs_lradc_adc_probe()
791 mxs_lradc_adc_hw_init(adc); in mxs_lradc_adc_probe()
803 mxs_lradc_adc_hw_stop(adc); in mxs_lradc_adc_probe()
813 struct mxs_lradc_adc *adc = iio_priv(iio); in mxs_lradc_adc_remove() local
816 mxs_lradc_adc_hw_stop(adc); in mxs_lradc_adc_remove()
825 .name = "mxs-lradc-adc",
833 MODULE_DESCRIPTION("Freescale MXS LRADC driver general purpose ADC driver");
835 MODULE_ALIAS("platform:mxs-lradc-adc");