42 #define STM32F7_I2C_CR2				0x04  macro
801 	cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_reload()
811 	writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_reload()
831 	cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_reload()
834 	writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_reload()
881 	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);  in stm32f7_i2c_xfer_msg()
949 	writel_relaxed(cr2, base + STM32F7_I2C_CR2);  in stm32f7_i2c_xfer_msg()
965 	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_xfer_msg()
1116 	writel_relaxed(cr2, base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_xfer_msg()
1128 	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_rep_start()
1202 	writel_relaxed(cr2, base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_rep_start()
1282 		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_slave_start()
1300 		stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_slave_start()
1446 			cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_slave_isr_event()
1448 			writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_slave_isr_event()
1451 			stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_slave_isr_event()
1552 			stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_isr_event()
1913 	stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);  in stm32f7_i2c_reg_slave()
2385 	backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_regs_backup()
2417 	writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_regs_restore()