41 #define STM32F7_I2C_CR1				0x00  macro
431 	stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_disable_irq()
723 	stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_disable_dma_req()
752 		stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_hw_config()
755 		stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_hw_config()
759 	stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_hw_config()
761 	stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_hw_config()
764 	stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_hw_config()
841 	stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_release_bus()
880 	cr1 = readl_relaxed(base + STM32F7_I2C_CR1);  in stm32f7_i2c_xfer_msg()
948 	writel_relaxed(cr1, base + STM32F7_I2C_CR1);  in stm32f7_i2c_xfer_msg()
966 	cr1 = readl_relaxed(base + STM32F7_I2C_CR1);  in stm32f7_i2c_smbus_xfer_msg()
1115 	writel_relaxed(cr1, base + STM32F7_I2C_CR1);  in stm32f7_i2c_smbus_xfer_msg()
1129 	cr1 = readl_relaxed(base + STM32F7_I2C_CR1);  in stm32f7_i2c_smbus_rep_start()
1201 	writel_relaxed(cr1, base + STM32F7_I2C_CR1);  in stm32f7_i2c_smbus_rep_start()
1285 		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_slave_start()
1290 		stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_slave_start()
1310 		stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_slave_start()
1834 		stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_enable_wakeup()
1837 		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_enable_wakeup()
1918 	stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);  in stm32f7_i2c_reg_slave()
2029 	stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);  in stm32f7_i2c_enable_smbus_host()
2040 		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,  in stm32f7_i2c_disable_smbus_host()
2064 	stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);  in stm32f7_i2c_enable_smbus_alert()
2076 		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,  in stm32f7_i2c_disable_smbus_alert()
2384 	backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);  in stm32f7_i2c_regs_backup()
2406 	cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);  in stm32f7_i2c_regs_restore()
2408 		stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_regs_restore()
2413 		       i2c_dev->base + STM32F7_I2C_CR1);  in stm32f7_i2c_regs_restore()
2415 		stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,  in stm32f7_i2c_regs_restore()