Lines Matching +full:exynos5260 +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
18 #include <linux/clk.h>
183 struct clk *clk; /* operating clock */ member
184 struct clk *pclk; /* bus clock */
200 /* Version of HS-I2C Hardware */
205 * struct exynos_hsi2c_variant - platform specific HSI2C driver data
240 .compatible = "samsung,exynos5-hsi2c",
243 .compatible = "samsung,exynos5250-hsi2c",
246 .compatible = "samsung,exynos5260-hsi2c",
249 .compatible = "samsung,exynos7-hsi2c",
252 .compatible = "samsung,exynosautov9-hsi2c",
260 writel(readl(i2c->regs + HSI2C_INT_STATUS), in exynos5_i2c_clr_pend_irq()
261 i2c->regs + HSI2C_INT_STATUS); in exynos5_i2c_clr_pend_irq()
271 * Returns 0 on success, -EINVAL if the cycle length cannot
286 unsigned int clkin = clk_get_rate(i2c->clk); in exynos5_i2c_set_timing()
287 unsigned int op_clk = hs_timings ? i2c->op_clock : in exynos5_i2c_set_timing()
288 (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) ? I2C_MAX_STANDARD_MODE_FREQ : in exynos5_i2c_set_timing()
289 i2c->op_clock; in exynos5_i2c_set_timing()
306 if (i2c->variant->hw == I2C_TYPE_EXYNOSAUTOV9) { in exynos5_i2c_set_timing()
307 div = ((clkin / (16 * i2c->op_clock)) - 1); in exynos5_i2c_set_timing()
310 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); in exynos5_i2c_set_timing()
312 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3); in exynos5_i2c_set_timing()
332 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7; in exynos5_i2c_set_timing()
333 temp = clkin / op_clk - 8 - t_ftl_cycle; in exynos5_i2c_set_timing()
334 if (i2c->variant->hw != I2C_TYPE_EXYNOS7) in exynos5_i2c_set_timing()
335 temp -= t_ftl_cycle; in exynos5_i2c_set_timing()
337 clk_cycle = temp / (div + 1) - 2; in exynos5_i2c_set_timing()
339 dev_err(i2c->dev, "%s clock set-up failed\n", in exynos5_i2c_set_timing()
341 return -EINVAL; in exynos5_i2c_set_timing()
358 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n", in exynos5_i2c_set_timing()
360 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n", in exynos5_i2c_set_timing()
362 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n", in exynos5_i2c_set_timing()
364 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd); in exynos5_i2c_set_timing()
367 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1); in exynos5_i2c_set_timing()
368 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2); in exynos5_i2c_set_timing()
369 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); in exynos5_i2c_set_timing()
371 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1); in exynos5_i2c_set_timing()
372 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2); in exynos5_i2c_set_timing()
373 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3); in exynos5_i2c_set_timing()
375 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA); in exynos5_i2c_set_timing()
385 if (ret < 0 || i2c->op_clock < I2C_MAX_FAST_MODE_PLUS_FREQ) in exynos5_hsi2c_clock_setup()
397 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF); in exynos5_i2c_init()
398 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT); in exynos5_i2c_init()
402 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT); in exynos5_i2c_init()
405 i2c->regs + HSI2C_CTL); in exynos5_i2c_init()
406 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL); in exynos5_i2c_init()
408 if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) { in exynos5_i2c_init()
409 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)), in exynos5_i2c_init()
410 i2c->regs + HSI2C_ADDR); in exynos5_i2c_init()
414 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF); in exynos5_i2c_init()
422 i2c_ctl = readl(i2c->regs + HSI2C_CTL); in exynos5_i2c_reset()
424 writel(i2c_ctl, i2c->regs + HSI2C_CTL); in exynos5_i2c_reset()
426 i2c_ctl = readl(i2c->regs + HSI2C_CTL); in exynos5_i2c_reset()
428 writel(i2c_ctl, i2c->regs + HSI2C_CTL); in exynos5_i2c_reset()
450 i2c->state = -EINVAL; in exynos5_i2c_irq()
452 spin_lock(&i2c->lock); in exynos5_i2c_irq()
454 int_status = readl(i2c->regs + HSI2C_INT_STATUS); in exynos5_i2c_irq()
455 writel(int_status, i2c->regs + HSI2C_INT_STATUS); in exynos5_i2c_irq()
458 switch (i2c->variant->hw) { in exynos5_i2c_irq()
463 i2c->trans_done = 1; in exynos5_i2c_irq()
464 i2c->state = 0; in exynos5_i2c_irq()
466 dev_dbg(i2c->dev, "Deal with arbitration lose\n"); in exynos5_i2c_irq()
467 i2c->state = -EAGAIN; in exynos5_i2c_irq()
470 dev_dbg(i2c->dev, "No ACK from device\n"); in exynos5_i2c_irq()
471 i2c->state = -ENXIO; in exynos5_i2c_irq()
474 dev_dbg(i2c->dev, "No device\n"); in exynos5_i2c_irq()
475 i2c->state = -ENXIO; in exynos5_i2c_irq()
478 dev_dbg(i2c->dev, "Accessing device timed out\n"); in exynos5_i2c_irq()
479 i2c->state = -ETIMEDOUT; in exynos5_i2c_irq()
488 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); in exynos5_i2c_irq()
490 dev_dbg(i2c->dev, "No ACK from device\n"); in exynos5_i2c_irq()
491 i2c->state = -ENXIO; in exynos5_i2c_irq()
494 dev_dbg(i2c->dev, "No device\n"); in exynos5_i2c_irq()
495 i2c->state = -ENXIO; in exynos5_i2c_irq()
498 dev_dbg(i2c->dev, "Deal with arbitration lose\n"); in exynos5_i2c_irq()
499 i2c->state = -EAGAIN; in exynos5_i2c_irq()
502 dev_dbg(i2c->dev, "Accessing device timed out\n"); in exynos5_i2c_irq()
503 i2c->state = -ETIMEDOUT; in exynos5_i2c_irq()
506 i2c->trans_done = 1; in exynos5_i2c_irq()
507 i2c->state = 0; in exynos5_i2c_irq()
513 if ((i2c->msg->flags & I2C_M_RD) && (int_status & in exynos5_i2c_irq()
515 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); in exynos5_i2c_irq()
517 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr); in exynos5_i2c_irq()
521 readl(i2c->regs + HSI2C_RX_DATA); in exynos5_i2c_irq()
522 i2c->msg->buf[i2c->msg_ptr++] = byte; in exynos5_i2c_irq()
523 len--; in exynos5_i2c_irq()
525 i2c->state = 0; in exynos5_i2c_irq()
527 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); in exynos5_i2c_irq()
530 len = i2c->variant->fifo_depth - fifo_level; in exynos5_i2c_irq()
531 if (len > (i2c->msg->len - i2c->msg_ptr)) { in exynos5_i2c_irq()
532 u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE); in exynos5_i2c_irq()
535 writel(int_en, i2c->regs + HSI2C_INT_ENABLE); in exynos5_i2c_irq()
536 len = i2c->msg->len - i2c->msg_ptr; in exynos5_i2c_irq()
540 byte = i2c->msg->buf[i2c->msg_ptr++]; in exynos5_i2c_irq()
541 writel(byte, i2c->regs + HSI2C_TX_DATA); in exynos5_i2c_irq()
542 len--; in exynos5_i2c_irq()
544 i2c->state = 0; in exynos5_i2c_irq()
548 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) || in exynos5_i2c_irq()
549 (i2c->state < 0)) { in exynos5_i2c_irq()
550 writel(0, i2c->regs + HSI2C_INT_ENABLE); in exynos5_i2c_irq()
552 complete(&i2c->msg_complete); in exynos5_i2c_irq()
555 spin_unlock(&i2c->lock); in exynos5_i2c_irq()
566 * Returns -EBUSY if the bus cannot be bought to idle
576 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); in exynos5_i2c_wait_bus_idle()
583 return -EBUSY; in exynos5_i2c_wait_bus_idle()
590 val = readl(i2c->regs + HSI2C_CTL) | HSI2C_RXCHON; in exynos5_i2c_bus_recover()
591 writel(val, i2c->regs + HSI2C_CTL); in exynos5_i2c_bus_recover()
592 val = readl(i2c->regs + HSI2C_CONF) & ~HSI2C_AUTO_MODE; in exynos5_i2c_bus_recover()
593 writel(val, i2c->regs + HSI2C_CONF); in exynos5_i2c_bus_recover()
600 writel(HSI2C_CMD_READ_DATA, i2c->regs + HSI2C_MANUAL_CMD); in exynos5_i2c_bus_recover()
602 writel(HSI2C_CMD_SEND_STOP, i2c->regs + HSI2C_MANUAL_CMD); in exynos5_i2c_bus_recover()
605 val = readl(i2c->regs + HSI2C_CTL) & ~HSI2C_RXCHON; in exynos5_i2c_bus_recover()
606 writel(val, i2c->regs + HSI2C_CTL); in exynos5_i2c_bus_recover()
607 val = readl(i2c->regs + HSI2C_CONF) | HSI2C_AUTO_MODE; in exynos5_i2c_bus_recover()
608 writel(val, i2c->regs + HSI2C_CONF); in exynos5_i2c_bus_recover()
615 if (i2c->variant->hw == I2C_TYPE_EXYNOS5) in exynos5_i2c_bus_check()
625 u32 st = readl(i2c->regs + HSI2C_TRANS_STATUS); in exynos5_i2c_bus_check()
657 if (i2c->variant->hw == I2C_TYPE_EXYNOS5) in exynos5_i2c_message_start()
662 i2c_ctl = readl(i2c->regs + HSI2C_CTL); in exynos5_i2c_message_start()
666 if (i2c->msg->flags & I2C_M_RD) { in exynos5_i2c_message_start()
671 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ? in exynos5_i2c_message_start()
672 (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len; in exynos5_i2c_message_start()
680 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ? in exynos5_i2c_message_start()
681 (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len; in exynos5_i2c_message_start()
687 i2c_addr = HSI2C_SLV_ADDR_MAS(i2c->msg->addr); in exynos5_i2c_message_start()
689 if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) in exynos5_i2c_message_start()
690 i2c_addr |= HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)); in exynos5_i2c_message_start()
692 writel(i2c_addr, i2c->regs + HSI2C_ADDR); in exynos5_i2c_message_start()
694 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL); in exynos5_i2c_message_start()
695 writel(i2c_ctl, i2c->regs + HSI2C_CTL); in exynos5_i2c_message_start()
703 spin_lock_irqsave(&i2c->lock, flags); in exynos5_i2c_message_start()
704 writel(int_en, i2c->regs + HSI2C_INT_ENABLE); in exynos5_i2c_message_start()
708 i2c_auto_conf |= i2c->msg->len; in exynos5_i2c_message_start()
710 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF); in exynos5_i2c_message_start()
711 spin_unlock_irqrestore(&i2c->lock, flags); in exynos5_i2c_message_start()
720 i2c->msg = msgs; in exynos5_i2c_xfer_msg()
721 i2c->msg_ptr = 0; in exynos5_i2c_xfer_msg()
722 i2c->trans_done = 0; in exynos5_i2c_xfer_msg()
724 reinit_completion(&i2c->msg_complete); in exynos5_i2c_xfer_msg()
728 timeout = wait_for_completion_timeout(&i2c->msg_complete, in exynos5_i2c_xfer_msg()
731 ret = -ETIMEDOUT; in exynos5_i2c_xfer_msg()
733 ret = i2c->state; in exynos5_i2c_xfer_msg()
744 if (ret == -ETIMEDOUT) in exynos5_i2c_xfer_msg()
745 dev_warn(i2c->dev, "%s timeout\n", in exynos5_i2c_xfer_msg()
746 (msgs->flags & I2C_M_RD) ? "rx" : "tx"); in exynos5_i2c_xfer_msg()
756 struct exynos5_i2c *i2c = adap->algo_data; in exynos5_i2c_xfer()
759 ret = clk_enable(i2c->pclk); in exynos5_i2c_xfer()
763 ret = clk_enable(i2c->clk); in exynos5_i2c_xfer()
773 clk_disable(i2c->clk); in exynos5_i2c_xfer()
775 clk_disable(i2c->pclk); in exynos5_i2c_xfer()
792 struct device_node *np = pdev->dev.of_node; in exynos5_i2c_probe()
796 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL); in exynos5_i2c_probe()
798 return -ENOMEM; in exynos5_i2c_probe()
800 if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock)) in exynos5_i2c_probe()
801 i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ; in exynos5_i2c_probe()
803 strscpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); in exynos5_i2c_probe()
804 i2c->adap.owner = THIS_MODULE; in exynos5_i2c_probe()
805 i2c->adap.algo = &exynos5_i2c_algorithm; in exynos5_i2c_probe()
806 i2c->adap.retries = 3; in exynos5_i2c_probe()
808 i2c->dev = &pdev->dev; in exynos5_i2c_probe()
809 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c"); in exynos5_i2c_probe()
810 if (IS_ERR(i2c->clk)) { in exynos5_i2c_probe()
811 dev_err(&pdev->dev, "cannot get clock\n"); in exynos5_i2c_probe()
812 return -ENOENT; in exynos5_i2c_probe()
815 i2c->pclk = devm_clk_get_optional(&pdev->dev, "hsi2c_pclk"); in exynos5_i2c_probe()
816 if (IS_ERR(i2c->pclk)) { in exynos5_i2c_probe()
817 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->pclk), in exynos5_i2c_probe()
821 ret = clk_prepare_enable(i2c->pclk); in exynos5_i2c_probe()
825 ret = clk_prepare_enable(i2c->clk); in exynos5_i2c_probe()
829 i2c->regs = devm_platform_ioremap_resource(pdev, 0); in exynos5_i2c_probe()
830 if (IS_ERR(i2c->regs)) { in exynos5_i2c_probe()
831 ret = PTR_ERR(i2c->regs); in exynos5_i2c_probe()
835 i2c->adap.dev.of_node = np; in exynos5_i2c_probe()
836 i2c->adap.algo_data = i2c; in exynos5_i2c_probe()
837 i2c->adap.dev.parent = &pdev->dev; in exynos5_i2c_probe()
839 /* Clear pending interrupts from u-boot or misc causes */ in exynos5_i2c_probe()
842 spin_lock_init(&i2c->lock); in exynos5_i2c_probe()
843 init_completion(&i2c->msg_complete); in exynos5_i2c_probe()
845 i2c->irq = ret = platform_get_irq(pdev, 0); in exynos5_i2c_probe()
849 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq, in exynos5_i2c_probe()
850 IRQF_NO_SUSPEND, dev_name(&pdev->dev), i2c); in exynos5_i2c_probe()
852 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq); in exynos5_i2c_probe()
856 i2c->variant = of_device_get_match_data(&pdev->dev); in exynos5_i2c_probe()
864 ret = i2c_add_adapter(&i2c->adap); in exynos5_i2c_probe()
870 clk_disable(i2c->clk); in exynos5_i2c_probe()
871 clk_disable(i2c->pclk); in exynos5_i2c_probe()
876 clk_disable_unprepare(i2c->clk); in exynos5_i2c_probe()
879 clk_disable_unprepare(i2c->pclk); in exynos5_i2c_probe()
887 i2c_del_adapter(&i2c->adap); in exynos5_i2c_remove()
889 clk_unprepare(i2c->clk); in exynos5_i2c_remove()
890 clk_unprepare(i2c->pclk); in exynos5_i2c_remove()
897 i2c_mark_adapter_suspended(&i2c->adap); in exynos5_i2c_suspend_noirq()
898 clk_unprepare(i2c->clk); in exynos5_i2c_suspend_noirq()
899 clk_unprepare(i2c->pclk); in exynos5_i2c_suspend_noirq()
909 ret = clk_prepare_enable(i2c->pclk); in exynos5_i2c_resume_noirq()
913 ret = clk_prepare_enable(i2c->clk); in exynos5_i2c_resume_noirq()
922 clk_disable(i2c->clk); in exynos5_i2c_resume_noirq()
923 clk_disable(i2c->pclk); in exynos5_i2c_resume_noirq()
924 i2c_mark_adapter_resumed(&i2c->adap); in exynos5_i2c_resume_noirq()
929 clk_disable_unprepare(i2c->clk); in exynos5_i2c_resume_noirq()
931 clk_disable_unprepare(i2c->pclk); in exynos5_i2c_resume_noirq()
944 .name = "exynos5-hsi2c",
952 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");