Lines Matching +full:24 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
24 ((2 << 24) | \
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
52 # define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24)
53 # define V3D_SLCACTL_T1CC_SHIFT 24
64 # define V3D_INT_SPILLUSE BIT(3)
65 # define V3D_INT_OUTOMEM BIT(2)
66 # define V3D_INT_FLDONE BIT(1)
67 # define V3D_INT_FRDONE BIT(0)
72 # define V3D_CTRSTA BIT(15)
73 # define V3D_CTSEMA BIT(12)
74 # define V3D_CTRTSD BIT(8)
75 # define V3D_CTRUN BIT(5)
76 # define V3D_CTSUBS BIT(4)
77 # define V3D_CTERR BIT(3)
78 # define V3D_CTMODE BIT(0)
97 # define V3D_BMOOM BIT(8)
98 # define V3D_RMBUSY BIT(3)
99 # define V3D_RMACTIVE BIT(2)
100 # define V3D_BMBUSY BIT(1)
101 # define V3D_BMACTIVE BIT(0)
121 # define V3D_PCTRE_EN BIT(31)
144 # define PV_CONTROL_CLR_AT_START BIT(14)
145 # define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13)
146 # define PV_CONTROL_WAIT_HSTART BIT(12)
154 # define PV_CONTROL_FIFO_CLR BIT(1)
155 # define PV_CONTROL_EN BIT(0)
160 # define PV_VCONTROL_ODD_FIRST BIT(5)
161 # define PV_VCONTROL_INTERLACE BIT(4)
162 # define PV_VCONTROL_DSI BIT(3)
163 # define PV_VCONTROL_COMMAND BIT(2)
164 # define PV_VCONTROL_CONTINUOUS BIT(1)
165 # define PV_VCONTROL_VIDEN BIT(0)
198 # define PV_INT_VID_IDLE BIT(9)
199 # define PV_INT_VFP_END BIT(8)
200 # define PV_INT_VFP_START BIT(7)
201 # define PV_INT_VACT_START BIT(6)
202 # define PV_INT_VBP_START BIT(5)
203 # define PV_INT_VSYNC_START BIT(4)
204 # define PV_INT_HFP_START BIT(3)
205 # define PV_INT_HACT_START BIT(2)
206 # define PV_INT_HBP_START BIT(1)
207 # define PV_INT_HSYNC_START BIT(0)
222 # define SCALER_DISPCTRL_ENABLE BIT(31)
223 # define SCALER_DISPCTRL_PANIC0_MASK VC4_MASK(25, 24)
224 # define SCALER_DISPCTRL_PANIC0_SHIFT 24
236 # define SCALER_DISPCTRL_DSPEISLUR(x) BIT(13 + (x))
237 # define SCALER5_DISPCTRL_DSPEISLUR(x) BIT(9 + ((x) * 4))
238 /* Enables Display 0 end-of-line-N contribution to
241 # define SCALER_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 2))
242 # define SCALER5_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 4))
244 # define SCALER_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 2))
245 # define SCALER5_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 4))
247 # define SCALER5_DISPCTRL_DSPEIVST(x) BIT(6 + ((x) * 4))
249 # define SCALER_DISPCTRL_SLVRDEIRQ BIT(6) /* HVS4 only */
250 # define SCALER_DISPCTRL_SLVWREIRQ BIT(5) /* HVS4 only */
251 # define SCALER5_DISPCTRL_SLVEIRQ BIT(5)
252 # define SCALER_DISPCTRL_DMAEIRQ BIT(4)
256 # define SCALER_DISPCTRL_DISPEIRQ(x) BIT(1 + (x))
258 # define SCALER_DISPCTRL_SCLEIRQ BIT(0)
268 # define SCALER_DISPSTAT_COBLOW(x) BIT(13 + ((x) * 8))
270 # define SCALER_DISPSTAT_EOLN(x) BIT(12 + ((x) * 8))
274 # define SCALER_DISPSTAT_ESFRAME(x) BIT(11 + ((x) * 8))
278 # define SCALER_DISPSTAT_ESLINE(x) BIT(10 + ((x) * 8))
282 # define SCALER_DISPSTAT_EUFLOW(x) BIT(9 + ((x) * 8))
284 # define SCALER_DISPSTAT_EOF(x) BIT(8 + ((x) * 8))
290 # define SCALER_DISPSTAT_DMA_ERROR BIT(7)
292 # define SCALER_DISPSTAT_IRQSLVRD BIT(6)
294 # define SCALER_DISPSTAT_IRQSLVWR BIT(5)
298 # define SCALER_DISPSTAT_IRQDMA BIT(4)
300 * corresponding interrupt bit is enabled in DISPCTRL.
302 # define SCALER_DISPSTAT_IRQDISP(x) BIT(1 + (x))
304 # define SCALER_DISPSTAT_IRQSCL BIT(0)
326 (x) * (SCALER_DISPLIST1 - \
333 (x) * (SCALER_DISPLACT1 - \
337 # define SCALER_DISPCTRLX_ENABLE BIT(31)
338 # define SCALER_DISPCTRLX_RESET BIT(30)
342 # define SCALER_DISPCTRLX_ONESHOT BIT(29)
346 # define SCALER_DISPCTRLX_ONECTX BIT(28)
348 # define SCALER_DISPCTRLX_FIFO32 BIT(27)
352 # define SCALER_DISPCTRLX_FIFOREG BIT(26)
364 # define SCALER5_DISPCTRLX_ONESHOT BIT(15)
374 # define SCALER_DISPBKGND_AUTOHS BIT(31)
375 # define SCALER5_DISPBKGND_BCK2BCK BIT(31)
376 # define SCALER_DISPBKGND_INTERLACE BIT(30)
377 # define SCALER_DISPBKGND_GAMMA BIT(29)
380 /* Enables filling the scaler line with the RGB value in the low 24
384 # define SCALER_DISPBKGND_FILL BIT(24)
393 # define SCALER_DISPSTATX_FULL BIT(29)
394 # define SCALER_DISPSTATX_EMPTY BIT(28)
400 * channel. Must be 4-pixel aligned (and thus 4 pixels less than the
406 * channel. Must be 4-pixel aligned.
414 (x) * (SCALER_DISPBKGND1 - \
423 (x) * (SCALER_DISPSTAT1 - \
428 (x) * (SCALER_DISPBASE1 - \
432 (x) * (SCALER_DISPCTRL1 - \
443 # define SCALER_GAMADDR_AUTOINC BIT(31)
447 # define SCALER_GAMADDR_SRAMENB BIT(30)
451 # define SCALER_OLEDOFFS_YUVCLAMP BIT(31)
454 # define SCALER_OLEDOFFS_DISPFIFO_MASK VC4_MASK(25, 24)
455 # define SCALER_OLEDOFFS_DISPFIFO_SHIFT 24
461 /* Offsets are 8-bit 2s-complement. */
500 # define SCALER_DISPSLAVE_ISSUE_VSTART BIT(31)
501 # define SCALER_DISPSLAVE_ISSUE_HSTART BIT(30)
503 # define SCALER_DISPSLAVE_EOL BIT(26)
505 # define SCALER_DISPSLAVE_EMPTY BIT(25)
507 # define SCALER_DISPSLAVE_VALID BIT(24)
517 # define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1)
518 # define VC4_HDMI_SW_RESET_HDMI BIT(0)
520 # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0)
522 # define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27)
523 # define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26)
527 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29)
528 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24)
529 # define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19)
530 # define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18)
534 # define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9)
536 # define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8)
570 # define VC4_HDMI_RAM_PACKET_ENABLE BIT(16)
575 # define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26)
577 # define VC4_HDMI_CRP_CFG_DISABLE BIT(25)
581 # define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24)
585 # define VC4_HDMI_HORZA_VPOS BIT(14)
586 # define VC4_HDMI_HORZA_HPOS BIT(13)
591 /* Horizontal pack porch (htotal - hsync_end). */
594 /* Horizontal sync pulse (hsync_end - hsync_start). */
597 /* Horizontal front porch (hsync_start - hdisplay). */
601 # define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14)
602 # define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13)
603 # define VC4_HDMI_FIFO_CTL_ON_VB BIT(7)
604 # define VC4_HDMI_FIFO_CTL_RECENTER BIT(6)
605 # define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5)
606 # define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4)
607 # define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3)
608 # define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2)
609 # define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1)
610 # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0)
613 # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15)
614 # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5)
615 # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3)
616 # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1)
617 # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0)
619 /* Vertical sync pulse (vsync_end - vsync_start). */
620 # define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20)
622 /* Vertical front porch (vsync_start - vdisplay). */
632 /* Vertical pack porch (vtotal - vsync_end). */
637 # define VC4_HDMI_CEC_TX_EOM BIT(31)
642 # define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30)
643 # define VC4_HDMI_CEC_RX_EOM BIT(29)
644 # define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28)
646 # define VC4_HDMI_CEC_REC_WRD_CNT_MASK VC4_MASK(27, 24)
647 # define VC4_HDMI_CEC_REC_WRD_CNT_SHIFT 24
655 # define VC4_HDMI_CEC_RX_CONTINUE BIT(23)
656 # define VC4_HDMI_CEC_TX_CONTINUE BIT(22)
658 # define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21)
662 # define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20)
668 /* Divides off of HSM clock to generate CEC bit clock. */
669 /* With the current defaults the CEC bit clock is 40 kHz = 25 usec */
673 /* Set these fields to how many bit clock cycles get to that many
676 # define VC4_HDMI_CEC_CNT_TO_1500_US_MASK VC4_MASK(30, 24)
677 # define VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT 24
687 # define VC4_HDMI_CEC_CNT_TO_2750_US_MASK VC4_MASK(31, 24)
688 # define VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT 24
696 # define VC4_HDMI_CEC_CNT_TO_4300_US_MASK VC4_MASK(31, 24)
697 # define VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT 24
705 # define VC4_HDMI_CEC_TX_SW_RESET BIT(27)
706 # define VC4_HDMI_CEC_RX_SW_RESET BIT(26)
707 # define VC4_HDMI_CEC_PAD_SW_RESET BIT(25)
708 # define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24)
709 # define VC4_HDMI_CEC_RX_CEC_INT BIT(23)
717 # define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25)
719 # define VC4_HDMI_CPU_CEC BIT(6)
720 # define VC4_HDMI_CPU_HOTPLUG BIT(0)
723 # define VC4_HD_CECRXD BIT(9)
725 # define VC4_HD_CECOVR BIT(8)
728 # define VC4_HD_M_SW_RST BIT(2)
729 # define VC4_HD_M_ENABLE BIT(0)
734 # define VC4_HD_MAI_CTL_DLATE BIT(15)
735 # define VC4_HD_MAI_CTL_BUSY BIT(14)
736 # define VC4_HD_MAI_CTL_CHALIGN BIT(13)
737 # define VC4_HD_MAI_CTL_WHOLSMP BIT(12)
738 # define VC4_HD_MAI_CTL_FULL BIT(11)
739 # define VC4_HD_MAI_CTL_EMPTY BIT(10)
740 # define VC4_HD_MAI_CTL_FLUSH BIT(9)
741 /* If set, MAI bus generates SPDIF (bit 31) parity instead of passing
744 # define VC4_HD_MAI_CTL_PAREN BIT(8)
747 # define VC4_HD_MAI_CTL_ENABLE BIT(3)
748 /* Underflow error status bit, write 1 to clear. */
749 # define VC4_HD_MAI_CTL_ERRORE BIT(2)
750 /* Overflow error status bit, write 1 to clear. */
751 # define VC4_HD_MAI_CTL_ERRORF BIT(1)
752 /* Single-shot reset bit. Read value is undefined. */
753 # define VC4_HD_MAI_CTL_RESET BIT(0)
755 # define VC4_HD_MAI_THR_PANICHIGH_MASK VC4_MASK(29, 24)
756 # define VC4_HD_MAI_THR_PANICHIGH_SHIFT 24
772 # define VC4_HD_VID_CTL_ENABLE BIT(31)
773 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30)
774 # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29)
775 # define VC4_HD_VID_CTL_VSYNC_LOW BIT(28)
776 # define VC4_HD_VID_CTL_HSYNC_LOW BIT(27)
777 # define VC4_HD_VID_CTL_CLRSYNC BIT(24)
778 # define VC4_HD_VID_CTL_CLRRGB BIT(23)
779 # define VC4_HD_VID_CTL_BLANKPIX BIT(18)
789 # define VC4_HD_CSC_CTL_PADMSB BIT(4)
795 # define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
796 # define VC4_HD_CSC_CTL_ENABLE BIT(0)
798 # define VC5_MT_CP_CSC_CTL_USE_444_TO_422 BIT(6)
803 # define VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION BIT(3)
804 # define VC5_MT_CP_CSC_CTL_ENABLE BIT(2)
812 # define VC4_DVP_HT_CLOCK_STOP_PIXEL BIT(1)
830 /* 24bpp */
863 /* For YCbCr modes (8-12, and 17) */
869 #define SCALER_CTL0_END BIT(31)
870 #define SCALER_CTL0_VALID BIT(30)
872 #define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24)
873 #define SCALER_CTL0_SIZE_SHIFT 24
882 #define SCALER_CTL0_ALPHA_MASK BIT(19)
883 #define SCALER_CTL0_HFLIP BIT(16)
884 #define SCALER_CTL0_VFLIP BIT(15)
903 #define SCALER5_CTL0_ALPHA_EXPAND BIT(12)
905 #define SCALER5_CTL0_RGB_EXPAND BIT(11)
923 #define SCALER_CTL0_UNITY BIT(4)
924 #define SCALER5_CTL0_UNITY BIT(15)
931 #define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)
932 #define SCALER_POS0_FIXED_ALPHA_SHIFT 24
946 #define SCALER5_POS0_VFLIP BIT(31)
947 #define SCALER5_POS0_HFLIP BIT(15)
956 #define SCALER5_CTL2_ALPHA_PREMULT BIT(29)
958 #define SCALER5_CTL2_ALPHA_MIX BIT(28)
960 #define SCALER5_CTL2_ALPHA_LOC BIT(25)
965 #define SCALER5_CTL2_GAMMA BIT(16)
988 #define SCALER_POS2_ALPHA_PREMULT BIT(29)
989 #define SCALER_POS2_ALPHA_MIX BIT(28)
1005 * 0x2: 2, 0x3: -1}
1008 #define SCALER_CSC0_COEF_CR_BLU_MASK VC4_MASK(31, 24)
1009 #define SCALER_CSC0_COEF_CR_BLU_SHIFT 24
1013 /* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */
1016 /* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */
1061 #define SCALER_TPZ0_VERT_RECALC BIT(31)
1072 #define SCALER_PPF_NOINTERP BIT(31)
1076 #define SCALER_PPF_AGC BIT(30)
1077 #define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8)
1084 #define SCALER_PPF_KERNEL_UNCACHED BIT(31)
1100 /* PITCH0 fields for T-tiled. */
1103 #define SCALER_PITCH0_TILE_LINE_DIR BIT(15)
1104 #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)