Lines Matching refs:afec0
716 u32 afec0 = DSI_PORT_READ(PHY_AFEC0); in vc4_dsi_latch_ulps() local
719 afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS); in vc4_dsi_latch_ulps()
721 afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS); in vc4_dsi_latch_ulps()
723 DSI_PORT_WRITE(PHY_AFEC0, afec0); in vc4_dsi_latch_ulps()
943 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | in vc4_dsi_bridge_pre_enable() local
947 afec0 |= DSI0_PHY_AFEC0_PD_DLANE1; in vc4_dsi_bridge_pre_enable()
950 afec0 |= DSI0_PHY_AFEC0_RESET; in vc4_dsi_bridge_pre_enable()
952 DSI_PORT_WRITE(PHY_AFEC0, afec0); in vc4_dsi_bridge_pre_enable()
962 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | in vc4_dsi_bridge_pre_enable() local
971 afec0 |= DSI1_PHY_AFEC0_PD_DLANE3; in vc4_dsi_bridge_pre_enable()
973 afec0 |= DSI1_PHY_AFEC0_PD_DLANE2; in vc4_dsi_bridge_pre_enable()
975 afec0 |= DSI1_PHY_AFEC0_PD_DLANE1; in vc4_dsi_bridge_pre_enable()
977 afec0 |= DSI1_PHY_AFEC0_RESET; in vc4_dsi_bridge_pre_enable()
979 DSI_PORT_WRITE(PHY_AFEC0, afec0); in vc4_dsi_bridge_pre_enable()