Lines Matching refs:DSI_PORT_WRITE
660 #define DSI_PORT_WRITE(offset, val) \ macro
723 DSI_PORT_WRITE(PHY_AFEC0, afec0); in vc4_dsi_latch_ulps()
752 DSI_PORT_WRITE(STAT, stat_ulps); in vc4_dsi_ulps()
753 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps); in vc4_dsi_ulps()
759 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps); in vc4_dsi_ulps()
771 DSI_PORT_WRITE(STAT, stat_stop); in vc4_dsi_ulps()
772 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps); in vc4_dsi_ulps()
778 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps); in vc4_dsi_ulps()
809 DSI_PORT_WRITE(DISP0_CTRL, disp0_ctrl); in vc4_dsi_bridge_disable()
930 DSI_PORT_WRITE(CTRL, in vc4_dsi_bridge_pre_enable()
934 DSI_PORT_WRITE(CTRL, in vc4_dsi_bridge_pre_enable()
939 DSI_PORT_WRITE(STAT, DSI_PORT_READ(STAT)); in vc4_dsi_bridge_pre_enable()
952 DSI_PORT_WRITE(PHY_AFEC0, afec0); in vc4_dsi_bridge_pre_enable()
957 DSI_PORT_WRITE(PHY_AFEC1, in vc4_dsi_bridge_pre_enable()
979 DSI_PORT_WRITE(PHY_AFEC0, afec0); in vc4_dsi_bridge_pre_enable()
981 DSI_PORT_WRITE(PHY_AFEC1, 0); in vc4_dsi_bridge_pre_enable()
1026 DSI_PORT_WRITE(HS_CLT0, in vc4_dsi_bridge_pre_enable()
1034 DSI_PORT_WRITE(HS_CLT1, in vc4_dsi_bridge_pre_enable()
1040 DSI_PORT_WRITE(HS_CLT2, in vc4_dsi_bridge_pre_enable()
1044 DSI_PORT_WRITE(HS_DLT3, in vc4_dsi_bridge_pre_enable()
1052 DSI_PORT_WRITE(HS_DLT4, in vc4_dsi_bridge_pre_enable()
1069 DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns, in vc4_dsi_bridge_pre_enable()
1073 DSI_PORT_WRITE(HS_DLT6, in vc4_dsi_bridge_pre_enable()
1079 DSI_PORT_WRITE(HS_DLT7, in vc4_dsi_bridge_pre_enable()
1083 DSI_PORT_WRITE(PHYC, in vc4_dsi_bridge_pre_enable()
1095 DSI_PORT_WRITE(CTRL, in vc4_dsi_bridge_pre_enable()
1100 DSI_PORT_WRITE(HSTX_TO_CNT, 0); in vc4_dsi_bridge_pre_enable()
1102 DSI_PORT_WRITE(LPRX_TO_CNT, 0xffffff); in vc4_dsi_bridge_pre_enable()
1104 DSI_PORT_WRITE(TA_TO_CNT, 100000); in vc4_dsi_bridge_pre_enable()
1106 DSI_PORT_WRITE(PR_TO_CNT, 100000); in vc4_dsi_bridge_pre_enable()
1111 DSI_PORT_WRITE(DISP1_CTRL, in vc4_dsi_bridge_pre_enable()
1118 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0); in vc4_dsi_bridge_pre_enable()
1120 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN); in vc4_dsi_bridge_pre_enable()
1123 DSI_PORT_WRITE(PHY_AFEC0, in vc4_dsi_bridge_pre_enable()
1130 DSI_PORT_WRITE(DISP0_CTRL, in vc4_dsi_bridge_pre_enable()
1138 DSI_PORT_WRITE(DISP0_CTRL, in vc4_dsi_bridge_pre_enable()
1152 DSI_PORT_WRITE(DISP0_CTRL, disp0_ctrl); in vc4_dsi_bridge_enable()
1221 DSI_PORT_WRITE(TXPKT_CMD_FIFO, packet.payload[i]); in vc4_dsi_host_transfer()
1225 DSI_PORT_WRITE(TXPKT_PIX_FIFO, in vc4_dsi_host_transfer()
1255 DSI_PORT_WRITE(INT_STAT, in vc4_dsi_host_transfer()
1258 DSI_PORT_WRITE(INT_EN, (DSI0_INTERRUPTS_ALWAYS_ENABLED | in vc4_dsi_host_transfer()
1261 DSI_PORT_WRITE(INT_EN, in vc4_dsi_host_transfer()
1267 DSI_PORT_WRITE(INT_STAT, in vc4_dsi_host_transfer()
1270 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED | in vc4_dsi_host_transfer()
1273 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED | in vc4_dsi_host_transfer()
1279 DSI_PORT_WRITE(TXPKT1H, pkth); in vc4_dsi_host_transfer()
1280 DSI_PORT_WRITE(TXPKT1C, pktc); in vc4_dsi_host_transfer()
1292 DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED)); in vc4_dsi_host_transfer()
1331 DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN); in vc4_dsi_host_transfer()
1333 DSI_PORT_WRITE(CTRL, in vc4_dsi_host_transfer()
1337 DSI_PORT_WRITE(TXPKT1C, 0); in vc4_dsi_host_transfer()
1338 DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED)); in vc4_dsi_host_transfer()
1502 DSI_PORT_WRITE(INT_STAT, stat); in vc4_dsi_irq_handler()
1724 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED); in vc4_dsi_bind()
1726 DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT)); in vc4_dsi_bind()