366 	unsigned int pll1;  member
770 	value = tegra_sor_readl(sor, sor->soc->regs->pll1);  in tegra_sor_dp_term_calibrate()
772 	tegra_sor_writel(sor, value, sor->soc->regs->pll1);  in tegra_sor_dp_term_calibrate()
777 		value = tegra_sor_readl(sor, sor->soc->regs->pll1);  in tegra_sor_dp_term_calibrate()
780 		tegra_sor_writel(sor, value, sor->soc->regs->pll1);  in tegra_sor_dp_term_calibrate()
784 		value = tegra_sor_readl(sor, sor->soc->regs->pll1);  in tegra_sor_dp_term_calibrate()
791 	value = tegra_sor_readl(sor, sor->soc->regs->pll1);  in tegra_sor_dp_term_calibrate()
794 	tegra_sor_writel(sor, value, sor->soc->regs->pll1);  in tegra_sor_dp_term_calibrate()
901 	value = tegra_sor_readl(sor, sor->soc->regs->pll1);  in tegra_sor_dp_link_configure()
918 	tegra_sor_writel(sor, value, sor->soc->regs->pll1);  in tegra_sor_dp_link_configure()
2500 	value = tegra_sor_readl(sor, sor->soc->regs->pll1);  in tegra_sor_hdmi_enable()
2506 	tegra_sor_writel(sor, value, sor->soc->regs->pll1);  in tegra_sor_hdmi_enable()
3282 	.pll1 = 0x18,
3454 	.pll1 = 0x18,
3515 	.pll1 = 0x164,
3598 	.pll1 = 0x16a,