Lines Matching full:value
486 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl() local
488 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
490 return value; in tegra_sor_readl()
493 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
496 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
497 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
544 u32 value; in tegra_clk_sor_pad_set_parent() local
546 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
547 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_clk_sor_pad_set_parent()
551 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_clk_sor_pad_set_parent()
555 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; in tegra_clk_sor_pad_set_parent()
559 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
569 u32 value; in tegra_clk_sor_pad_get_parent() local
571 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_get_parent()
573 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) { in tegra_clk_sor_pad_get_parent()
647 u32 value; in tegra_sor_power_up_lanes() local
653 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
656 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
659 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
663 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
665 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
668 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
670 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
672 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
675 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_power_up_lanes()
677 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
682 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
683 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_power_up_lanes()
689 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) in tegra_sor_power_up_lanes()
698 u32 value; in tegra_sor_power_down_lanes() local
701 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
702 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_power_down_lanes()
704 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
707 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | in tegra_sor_power_down_lanes()
709 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
714 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
715 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_power_down_lanes()
721 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) in tegra_sor_power_down_lanes()
729 u32 value; in tegra_sor_dp_precharge() local
732 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
735 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
738 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
742 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
744 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
747 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
749 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
751 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
755 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
756 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | in tegra_sor_dp_precharge()
758 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
763 u32 mask = 0x08, adj = 0, value; in tegra_sor_dp_term_calibrate() local
766 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
767 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_dp_term_calibrate()
768 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
770 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
771 value |= SOR_PLL1_TMDS_TERM; in tegra_sor_dp_term_calibrate()
772 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
777 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
778 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_dp_term_calibrate()
779 value |= SOR_PLL1_TMDS_TERMADJ(adj); in tegra_sor_dp_term_calibrate()
780 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
784 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
785 if (value & SOR_PLL1_TERM_COMPOUT) in tegra_sor_dp_term_calibrate()
791 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
792 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_dp_term_calibrate()
793 value |= SOR_PLL1_TMDS_TERMADJ(adj); in tegra_sor_dp_term_calibrate()
794 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
797 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
798 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_dp_term_calibrate()
799 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
807 u32 pattern = 0, tx_pu = 0, value; in tegra_sor_dp_link_apply_training() local
810 for (value = 0, i = 0; i < link->lanes; i++) { in tegra_sor_dp_link_apply_training()
825 value = SOR_DP_TPG_SCRAMBLER_GALIOS | in tegra_sor_dp_link_apply_training()
830 value = SOR_DP_TPG_SCRAMBLER_NONE | in tegra_sor_dp_link_apply_training()
835 value = SOR_DP_TPG_SCRAMBLER_NONE | in tegra_sor_dp_link_apply_training()
840 value = SOR_DP_TPG_SCRAMBLER_NONE | in tegra_sor_dp_link_apply_training()
849 value |= SOR_DP_TPG_CHANNEL_CODING; in tegra_sor_dp_link_apply_training()
851 pattern = pattern << 8 | value; in tegra_sor_dp_link_apply_training()
862 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
863 value &= ~SOR_DP_PADCTL_TX_PU_MASK; in tegra_sor_dp_link_apply_training()
864 value |= SOR_DP_PADCTL_TX_PU_ENABLE; in tegra_sor_dp_link_apply_training()
865 value |= SOR_DP_PADCTL_TX_PU(tx_pu); in tegra_sor_dp_link_apply_training()
866 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
877 u32 value; in tegra_sor_dp_link_configure() local
884 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
885 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_dp_link_configure()
886 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); in tegra_sor_dp_link_configure()
887 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
889 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_dp_link_configure()
890 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_dp_link_configure()
891 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); in tegra_sor_dp_link_configure()
894 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; in tegra_sor_dp_link_configure()
896 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_dp_link_configure()
901 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
902 value &= ~SOR_PLL1_LOADADJ_MASK; in tegra_sor_dp_link_configure()
906 value |= SOR_PLL1_LOADADJ(0x3); in tegra_sor_dp_link_configure()
910 value |= SOR_PLL1_LOADADJ(0x4); in tegra_sor_dp_link_configure()
914 value |= SOR_PLL1_LOADADJ(0x6); in tegra_sor_dp_link_configure()
918 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
921 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_link_configure()
924 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_link_configure()
926 value |= SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_link_configure()
928 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_link_configure()
970 u32 value; in tegra_sor_setup_pwm() local
972 value = tegra_sor_readl(sor, SOR_PWM_DIV); in tegra_sor_setup_pwm()
973 value &= ~SOR_PWM_DIV_MASK; in tegra_sor_setup_pwm()
974 value |= 0x400; /* period */ in tegra_sor_setup_pwm()
975 tegra_sor_writel(sor, value, SOR_PWM_DIV); in tegra_sor_setup_pwm()
977 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
978 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; in tegra_sor_setup_pwm()
979 value |= 0x400; /* duty cycle */ in tegra_sor_setup_pwm()
980 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ in tegra_sor_setup_pwm()
981 value |= SOR_PWM_CTL_TRIGGER; in tegra_sor_setup_pwm()
982 tegra_sor_writel(sor, value, SOR_PWM_CTL); in tegra_sor_setup_pwm()
987 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
988 if ((value & SOR_PWM_CTL_TRIGGER) == 0) in tegra_sor_setup_pwm()
999 unsigned long value, timeout; in tegra_sor_attach() local
1002 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
1003 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; in tegra_sor_attach()
1004 value |= SOR_SUPER_STATE_MODE_NORMAL; in tegra_sor_attach()
1005 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
1009 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
1010 value |= SOR_SUPER_STATE_ATTACHED; in tegra_sor_attach()
1011 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
1017 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_attach()
1018 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_attach()
1029 unsigned long value, timeout; in tegra_sor_wakeup() local
1035 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_wakeup()
1036 value &= SOR_TEST_HEAD_MODE_MASK; in tegra_sor_wakeup()
1038 if (value == SOR_TEST_HEAD_MODE_AWAKE) in tegra_sor_wakeup()
1049 u32 value; in tegra_sor_power_up() local
1051 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
1052 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; in tegra_sor_power_up()
1053 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_up()
1058 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
1059 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_up()
1246 u32 value; in tegra_sor_apply_config() local
1248 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1249 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; in tegra_sor_apply_config()
1250 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); in tegra_sor_apply_config()
1251 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1253 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1254 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; in tegra_sor_apply_config()
1255 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); in tegra_sor_apply_config()
1257 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; in tegra_sor_apply_config()
1258 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); in tegra_sor_apply_config()
1260 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; in tegra_sor_apply_config()
1261 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); in tegra_sor_apply_config()
1264 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; in tegra_sor_apply_config()
1266 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; in tegra_sor_apply_config()
1268 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; in tegra_sor_apply_config()
1269 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; in tegra_sor_apply_config()
1270 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1272 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1273 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; in tegra_sor_apply_config()
1274 value |= config->hblank_symbols & 0xffff; in tegra_sor_apply_config()
1275 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1277 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1278 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; in tegra_sor_apply_config()
1279 value |= config->vblank_symbols & 0xffff; in tegra_sor_apply_config()
1280 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1289 u32 value; in tegra_sor_mode_set() local
1291 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_mode_set()
1292 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; in tegra_sor_mode_set()
1293 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; in tegra_sor_mode_set()
1294 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_mode_set()
1296 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | in tegra_sor_mode_set()
1300 value &= ~SOR_STATE_ASY_HSYNCPOL; in tegra_sor_mode_set()
1303 value |= SOR_STATE_ASY_HSYNCPOL; in tegra_sor_mode_set()
1306 value &= ~SOR_STATE_ASY_VSYNCPOL; in tegra_sor_mode_set()
1309 value |= SOR_STATE_ASY_VSYNCPOL; in tegra_sor_mode_set()
1313 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444; in tegra_sor_mode_set()
1317 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444; in tegra_sor_mode_set()
1321 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444; in tegra_sor_mode_set()
1325 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; in tegra_sor_mode_set()
1329 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; in tegra_sor_mode_set()
1333 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; in tegra_sor_mode_set()
1337 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_mode_set()
1344 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); in tegra_sor_mode_set()
1345 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); in tegra_sor_mode_set()
1351 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); in tegra_sor_mode_set()
1352 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); in tegra_sor_mode_set()
1358 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); in tegra_sor_mode_set()
1359 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); in tegra_sor_mode_set()
1365 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); in tegra_sor_mode_set()
1366 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); in tegra_sor_mode_set()
1374 unsigned long value, timeout; in tegra_sor_detach() local
1377 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1378 value &= ~SOR_SUPER_STATE_MODE_NORMAL; in tegra_sor_detach()
1379 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1385 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_detach()
1386 if (value & SOR_PWR_MODE_SAFE) in tegra_sor_detach()
1390 if ((value & SOR_PWR_MODE_SAFE) == 0) in tegra_sor_detach()
1394 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1395 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; in tegra_sor_detach()
1396 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1400 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1401 value &= ~SOR_SUPER_STATE_ATTACHED; in tegra_sor_detach()
1402 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1408 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_detach()
1409 if ((value & SOR_TEST_ATTACHED) == 0) in tegra_sor_detach()
1415 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_detach()
1423 unsigned long value, timeout; in tegra_sor_power_down() local
1426 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1427 value &= ~SOR_PWR_NORMAL_STATE_PU; in tegra_sor_power_down()
1428 value |= SOR_PWR_TRIGGER; in tegra_sor_power_down()
1429 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_down()
1434 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1435 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_down()
1441 if ((value & SOR_PWR_TRIGGER) != 0) in tegra_sor_power_down()
1451 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1452 value |= SOR_PLL2_PORT_POWERDOWN; in tegra_sor_power_down()
1453 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1457 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1458 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; in tegra_sor_power_down()
1459 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1461 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1462 value |= SOR_PLL2_SEQ_PLLCAPPD; in tegra_sor_power_down()
1463 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_power_down()
1464 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1473 u32 value; in tegra_sor_crc_wait() local
1478 value = tegra_sor_readl(sor, SOR_CRCA); in tegra_sor_crc_wait()
1479 if (value & SOR_CRCA_VALID) in tegra_sor_crc_wait()
1495 u32 value; in tegra_sor_show_crc() local
1504 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_show_crc()
1505 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; in tegra_sor_show_crc()
1506 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_show_crc()
1508 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1509 value |= SOR_CRC_CNTRL_ENABLE; in tegra_sor_show_crc()
1510 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1512 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_show_crc()
1513 value &= ~SOR_TEST_CRC_POST_SERIALIZE; in tegra_sor_show_crc()
1514 tegra_sor_writel(sor, value, SOR_TEST); in tegra_sor_show_crc()
1521 value = tegra_sor_readl(sor, SOR_CRCB); in tegra_sor_show_crc()
1523 seq_printf(s, "%08x\n", value); in tegra_sor_show_crc()
1850 u32 value = 0; in tegra_sor_hdmi_subpack() local
1854 value = (value << 8) | ptr[i - 1]; in tegra_sor_hdmi_subpack()
1856 return value; in tegra_sor_hdmi_subpack()
1865 u32 value; in tegra_sor_hdmi_write_infopack() local
1886 value = INFOFRAME_HEADER_TYPE(ptr[0]) | in tegra_sor_hdmi_write_infopack()
1889 tegra_sor_writel(sor, value, offset); in tegra_sor_hdmi_write_infopack()
1900 value = tegra_sor_hdmi_subpack(&ptr[i], num); in tegra_sor_hdmi_write_infopack()
1901 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1905 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); in tegra_sor_hdmi_write_infopack()
1906 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1916 u32 value; in tegra_sor_hdmi_setup_avi_infoframe() local
1920 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1921 value &= ~INFOFRAME_CTRL_SINGLE; in tegra_sor_hdmi_setup_avi_infoframe()
1922 value &= ~INFOFRAME_CTRL_OTHER; in tegra_sor_hdmi_setup_avi_infoframe()
1923 value &= ~INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
1924 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1942 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1943 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
1944 value |= INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
1945 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1970 u32 value; in tegra_sor_audio_prepare() local
1977 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0; in tegra_sor_audio_prepare()
1978 tegra_sor_writel(sor, value, SOR_INT_ENABLE); in tegra_sor_audio_prepare()
1979 tegra_sor_writel(sor, value, SOR_INT_MASK); in tegra_sor_audio_prepare()
1983 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD; in tegra_sor_audio_prepare()
1984 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE); in tegra_sor_audio_prepare()
1996 u32 value; in tegra_sor_audio_enable() local
1998 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); in tegra_sor_audio_enable()
2001 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK); in tegra_sor_audio_enable()
2002 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA); in tegra_sor_audio_enable()
2006 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL; in tegra_sor_audio_enable()
2008 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL; in tegra_sor_audio_enable()
2010 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH; in tegra_sor_audio_enable()
2012 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); in tegra_sor_audio_enable()
2022 u32 value; in tegra_sor_hdmi_enable_audio_infoframe() local
2041 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2042 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; in tegra_sor_hdmi_enable_audio_infoframe()
2043 value |= INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_enable_audio_infoframe()
2044 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2051 u32 value; in tegra_sor_hdmi_audio_enable() local
2057 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH | in tegra_sor_hdmi_audio_enable()
2060 tegra_sor_writel(sor, value, SOR_HDMI_SPARE); in tegra_sor_hdmi_audio_enable()
2063 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0); in tegra_sor_hdmi_audio_enable()
2064 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW); in tegra_sor_hdmi_audio_enable()
2067 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE; in tegra_sor_hdmi_audio_enable()
2068 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH); in tegra_sor_hdmi_audio_enable()
2071 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP; in tegra_sor_hdmi_audio_enable()
2072 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2074 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2075 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); in tegra_sor_hdmi_audio_enable()
2087 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2088 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); in tegra_sor_hdmi_audio_enable()
2091 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2092 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); in tegra_sor_hdmi_audio_enable()
2095 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2096 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); in tegra_sor_hdmi_audio_enable()
2099 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2100 value &= ~SOR_HDMI_AUDIO_N_RESET; in tegra_sor_hdmi_audio_enable()
2101 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2108 u32 value; in tegra_sor_hdmi_disable_audio_infoframe() local
2110 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2111 value &= ~INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_disable_audio_infoframe()
2112 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2134 u32 value; in tegra_sor_hdmi_disable_scrambling() local
2136 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2137 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; in tegra_sor_hdmi_disable_scrambling()
2138 value &= ~SOR_HDMI2_CTRL_SCRAMBLE; in tegra_sor_hdmi_disable_scrambling()
2139 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2160 u32 value; in tegra_sor_hdmi_enable_scrambling() local
2162 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2163 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; in tegra_sor_hdmi_enable_scrambling()
2164 value |= SOR_HDMI2_CTRL_SCRAMBLE; in tegra_sor_hdmi_enable_scrambling()
2165 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2207 u32 value; in tegra_sor_hdmi_disable() local
2221 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2224 value &= ~SOR1_TIMING_CYA; in tegra_sor_hdmi_disable()
2226 value &= ~SOR_ENABLE(sor->index); in tegra_sor_hdmi_disable()
2228 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2254 u32 value; in tegra_sor_hdmi_enable() local
2282 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2283 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_hdmi_enable()
2284 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2288 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2289 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; in tegra_sor_hdmi_enable()
2290 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2292 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2293 value &= ~SOR_PLL0_VCOPD; in tegra_sor_hdmi_enable()
2294 value &= ~SOR_PLL0_PWR; in tegra_sor_hdmi_enable()
2295 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2297 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2298 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_hdmi_enable()
2299 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2303 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2304 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; in tegra_sor_hdmi_enable()
2305 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_hdmi_enable()
2306 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2310 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2311 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_hdmi_enable()
2313 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2316 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2317 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) in tegra_sor_hdmi_enable()
2323 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_hdmi_enable()
2325 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2328 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2329 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_hdmi_enable()
2335 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2336 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_hdmi_enable()
2337 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_sor_hdmi_enable()
2341 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; in tegra_sor_hdmi_enable()
2344 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; in tegra_sor_hdmi_enable()
2347 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_sor_hdmi_enable()
2348 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2353 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2354 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_hdmi_enable()
2355 value |= SOR_DP_LINKCTL_LANE_COUNT(4); in tegra_sor_hdmi_enable()
2356 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2358 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2359 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; in tegra_sor_hdmi_enable()
2360 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_hdmi_enable()
2361 value &= ~SOR_DP_SPARE_SEQ_ENABLE; in tegra_sor_hdmi_enable()
2362 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK; in tegra_sor_hdmi_enable()
2363 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2365 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | in tegra_sor_hdmi_enable()
2367 tegra_sor_writel(sor, value, SOR_SEQ_CTL); in tegra_sor_hdmi_enable()
2369 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | in tegra_sor_hdmi_enable()
2371 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); in tegra_sor_hdmi_enable()
2372 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); in tegra_sor_hdmi_enable()
2376 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); in tegra_sor_hdmi_enable()
2377 tegra_sor_writel(sor, value, SOR_REFCLK); in tegra_sor_hdmi_enable()
2381 for (value = 0, i = 0; i < 5; i++) in tegra_sor_hdmi_enable()
2382 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | in tegra_sor_hdmi_enable()
2386 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_hdmi_enable()
2430 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); in tegra_sor_hdmi_enable()
2434 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; in tegra_sor_hdmi_enable()
2436 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); in tegra_sor_hdmi_enable()
2441 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | in tegra_sor_hdmi_enable()
2443 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); in tegra_sor_hdmi_enable()
2451 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | in tegra_sor_hdmi_enable()
2453 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_sor_hdmi_enable()
2455 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); in tegra_sor_hdmi_enable()
2456 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_sor_hdmi_enable()
2458 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2459 value |= H_PULSE2_ENABLE; in tegra_sor_hdmi_enable()
2460 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2472 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2473 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_hdmi_enable()
2474 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; in tegra_sor_hdmi_enable()
2475 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2478 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2479 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_hdmi_enable()
2480 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2490 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2491 value &= ~SOR_PLL0_ICHPMP_MASK; in tegra_sor_hdmi_enable()
2492 value &= ~SOR_PLL0_FILTER_MASK; in tegra_sor_hdmi_enable()
2493 value &= ~SOR_PLL0_VCOCAP_MASK; in tegra_sor_hdmi_enable()
2494 value |= SOR_PLL0_ICHPMP(settings->ichpmp); in tegra_sor_hdmi_enable()
2495 value |= SOR_PLL0_FILTER(settings->filter); in tegra_sor_hdmi_enable()
2496 value |= SOR_PLL0_VCOCAP(settings->vcocap); in tegra_sor_hdmi_enable()
2497 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2500 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2501 value &= ~SOR_PLL1_LOADADJ_MASK; in tegra_sor_hdmi_enable()
2502 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_hdmi_enable()
2503 value |= SOR_PLL1_LOADADJ(settings->loadadj); in tegra_sor_hdmi_enable()
2504 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); in tegra_sor_hdmi_enable()
2505 value |= SOR_PLL1_TMDS_TERM; in tegra_sor_hdmi_enable()
2506 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2508 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2509 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK; in tegra_sor_hdmi_enable()
2510 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; in tegra_sor_hdmi_enable()
2511 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK; in tegra_sor_hdmi_enable()
2512 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK; in tegra_sor_hdmi_enable()
2513 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); in tegra_sor_hdmi_enable()
2514 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); in tegra_sor_hdmi_enable()
2515 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); in tegra_sor_hdmi_enable()
2516 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); in tegra_sor_hdmi_enable()
2517 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2519 value = settings->drive_current[3] << 24 | in tegra_sor_hdmi_enable()
2523 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_hdmi_enable()
2525 value = settings->preemphasis[3] << 24 | in tegra_sor_hdmi_enable()
2529 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_hdmi_enable()
2531 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2532 value &= ~SOR_DP_PADCTL_TX_PU_MASK; in tegra_sor_hdmi_enable()
2533 value |= SOR_DP_PADCTL_TX_PU_ENABLE; in tegra_sor_hdmi_enable()
2534 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); in tegra_sor_hdmi_enable()
2535 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2537 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2538 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK; in tegra_sor_hdmi_enable()
2539 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); in tegra_sor_hdmi_enable()
2540 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2543 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2544 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_hdmi_enable()
2545 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2549 value = VSYNC_H_POSITION(1); in tegra_sor_hdmi_enable()
2550 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); in tegra_sor_hdmi_enable()
2553 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2554 value &= ~DITHER_CONTROL_MASK; in tegra_sor_hdmi_enable()
2555 value &= ~BASE_COLOR_SIZE_MASK; in tegra_sor_hdmi_enable()
2559 value |= BASE_COLOR_SIZE_666; in tegra_sor_hdmi_enable()
2563 value |= BASE_COLOR_SIZE_888; in tegra_sor_hdmi_enable()
2567 value |= BASE_COLOR_SIZE_101010; in tegra_sor_hdmi_enable()
2571 value |= BASE_COLOR_SIZE_121212; in tegra_sor_hdmi_enable()
2576 value |= BASE_COLOR_SIZE_888; in tegra_sor_hdmi_enable()
2580 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2583 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2584 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_hdmi_enable()
2585 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); in tegra_sor_hdmi_enable()
2586 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2593 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2594 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; in tegra_sor_hdmi_enable()
2595 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; in tegra_sor_hdmi_enable()
2596 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2599 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2600 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; in tegra_sor_hdmi_enable()
2601 value |= SOR_HEAD_STATE_COLORSPACE_RGB; in tegra_sor_hdmi_enable()
2602 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2609 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2610 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; in tegra_sor_hdmi_enable()
2611 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2618 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2621 value |= SOR1_TIMING_CYA; in tegra_sor_hdmi_enable()
2623 value |= SOR_ENABLE(sor->index); in tegra_sor_hdmi_enable()
2625 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2628 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2629 value &= ~PROTOCOL_MASK; in tegra_sor_hdmi_enable()
2630 value |= PROTOCOL_SINGLE_TMDS_A; in tegra_sor_hdmi_enable()
2631 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2655 u32 value; in tegra_sor_dp_disable() local
2679 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_disable()
2680 value &= ~SOR_ENABLE(sor->index); in tegra_sor_dp_disable()
2681 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_disable()
2684 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_dp_disable()
2685 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_dp_disable()
2686 value &= ~SOR_STATE_ASY_SUBOWNER_MASK; in tegra_sor_dp_disable()
2687 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_dp_disable()
2688 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_dp_disable()
2724 u32 value; in tegra_sor_dp_enable() local
2765 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2766 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_dp_enable()
2767 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2771 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2772 value |= SOR_PLL3_PLL_VDD_MODE_3V3; in tegra_sor_dp_enable()
2773 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2775 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2776 value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR); in tegra_sor_dp_enable()
2777 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2779 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2780 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_dp_enable()
2781 value |= SOR_PLL2_SEQ_PLLCAPPD; in tegra_sor_dp_enable()
2782 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2786 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2787 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; in tegra_sor_dp_enable()
2788 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_dp_enable()
2789 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2791 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_dp_enable()
2792 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_sor_dp_enable()
2795 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; in tegra_sor_dp_enable()
2797 value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK; in tegra_sor_dp_enable()
2799 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_enable()
2803 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_enable()
2806 value |= SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_enable()
2808 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_enable()
2810 value |= SOR_DP_SPARE_SEQ_ENABLE; in tegra_sor_dp_enable()
2811 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_enable()
2816 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2817 value &= ~SOR_PLL0_ICHPMP_MASK; in tegra_sor_dp_enable()
2818 value &= ~SOR_PLL0_VCOCAP_MASK; in tegra_sor_dp_enable()
2819 value |= SOR_PLL0_ICHPMP(0x1); in tegra_sor_dp_enable()
2820 value |= SOR_PLL0_VCOCAP(0x3); in tegra_sor_dp_enable()
2821 value |= SOR_PLL0_RESISTOR_EXT; in tegra_sor_dp_enable()
2822 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2825 for (value = 0, i = 0; i < 5; i++) in tegra_sor_dp_enable()
2826 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | in tegra_sor_dp_enable()
2830 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_dp_enable()
2864 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_dp_enable()
2865 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_dp_enable()
2866 value |= SOR_STATE_ASY_PROTOCOL_DP_A; in tegra_sor_dp_enable()
2867 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_dp_enable()
2870 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_dp_enable()
2871 value |= SOR_DP_LINKCTL_ENABLE; in tegra_sor_dp_enable()
2872 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_dp_enable()
2899 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | in tegra_sor_dp_enable()
2901 tegra_sor_writel(sor, value, SOR_CSTM); in tegra_sor_dp_enable()
2920 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_enable()
2921 value |= SOR_ENABLE(sor->index); in tegra_sor_dp_enable()
2922 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_enable()
3642 u32 value; in tegra_sor_parse_dt() local
3646 err = of_property_read_u32(np, "nvidia,interface", &value); in tegra_sor_parse_dt()
3650 sor->index = value; in tegra_sor_parse_dt()
3681 u32 value; in tegra_sor_irq() local
3683 value = tegra_sor_readl(sor, SOR_INT_STATUS); in tegra_sor_irq()
3684 tegra_sor_writel(sor, value, SOR_INT_STATUS); in tegra_sor_irq()
3686 if (value & SOR_INT_CODEC_SCRATCH0) { in tegra_sor_irq()
3687 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); in tegra_sor_irq()
3689 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) { in tegra_sor_irq()
3692 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK; in tegra_sor_irq()