Lines Matching +full:tegra186 +full:- +full:display
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
19 #include <drm/display/drm_dp_helper.h>
20 #include <drm/display/drm_scdc_helper.h>
486 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()
488 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
496 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
497 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
504 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock()
506 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock()
510 err = clk_prepare_enable(sor->clk); in tegra_sor_set_parent_clock()
533 * Implementing ->set_parent() here isn't really required because the parent
536 * Tegra186 and later SoC generations where the BPMP implements this clock
543 struct tegra_sor *sor = pad->sor; in tegra_clk_sor_pad_set_parent()
567 struct tegra_sor *sor = pad->sor; in tegra_clk_sor_pad_get_parent()
601 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL); in tegra_clk_sor_pad_register()
603 return ERR_PTR(-ENOMEM); in tegra_clk_sor_pad_register()
605 pad->sor = sor; in tegra_clk_sor_pad_register()
609 init.parent_names = tegra_clk_sor_pad_parents[sor->index]; in tegra_clk_sor_pad_register()
610 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]); in tegra_clk_sor_pad_register()
613 pad->hw.init = &init; in tegra_clk_sor_pad_register()
615 clk = devm_clk_register(sor->dev, &pad->hw); in tegra_clk_sor_pad_register()
622 struct drm_dp_link *link = &sor->link; in tegra_sor_filter_rates()
626 for (i = 0; i < link->num_rates; i++) { in tegra_sor_filter_rates()
627 switch (link->rates[i]) { in tegra_sor_filter_rates()
635 link->rates[i]); in tegra_sor_filter_rates()
636 link->rates[i] = 0; in tegra_sor_filter_rates()
653 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
656 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
657 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2])); in tegra_sor_power_up_lanes()
659 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
660 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]); in tegra_sor_power_up_lanes()
663 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
665 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
668 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
670 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
672 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
690 return -ETIMEDOUT; in tegra_sor_power_up_lanes()
701 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
704 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
722 return -ETIMEDOUT; in tegra_sor_power_down_lanes()
731 /* pre-charge all used lanes */ in tegra_sor_dp_precharge()
732 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
735 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
736 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2])); in tegra_sor_dp_precharge()
738 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
739 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]); in tegra_sor_dp_precharge()
742 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
744 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
747 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
749 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
751 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
755 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
758 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
766 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
768 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
770 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
772 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
777 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
780 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
784 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
791 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
794 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
797 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
799 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
806 const struct tegra_sor_soc *soc = sor->soc; in tegra_sor_dp_link_apply_training()
810 for (value = 0, i = 0; i < link->lanes; i++) { in tegra_sor_dp_link_apply_training()
811 u8 vs = link->train.request.voltage_swing[i]; in tegra_sor_dp_link_apply_training()
812 u8 pe = link->train.request.pre_emphasis[i]; in tegra_sor_dp_link_apply_training()
813 u8 pc = link->train.request.post_cursor[i]; in tegra_sor_dp_link_apply_training()
814 u8 shift = sor->soc->lane_map[i] << 3; in tegra_sor_dp_link_apply_training()
816 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift; in tegra_sor_dp_link_apply_training()
817 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift; in tegra_sor_dp_link_apply_training()
818 post_cursor |= soc->post_cursor[pc][vs][pe] << shift; in tegra_sor_dp_link_apply_training()
820 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu) in tegra_sor_dp_link_apply_training()
821 tx_pu = sor->soc->tx_pu[pc][vs][pe]; in tegra_sor_dp_link_apply_training()
823 switch (link->train.pattern) { in tegra_sor_dp_link_apply_training()
845 return -EINVAL; in tegra_sor_dp_link_apply_training()
848 if (link->caps.channel_coding) in tegra_sor_dp_link_apply_training()
857 if (link->caps.tps3_supported) in tegra_sor_dp_link_apply_training()
862 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
866 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
880 rate = drm_dp_link_rate_to_bw_code(link->rate); in tegra_sor_dp_link_configure()
881 lanes = link->lanes; in tegra_sor_dp_link_configure()
893 if (link->caps.enhanced_framing) in tegra_sor_dp_link_configure()
901 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
918 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
923 if (link->edp == 0) in tegra_sor_dp_link_configure()
932 dev_err(sor->dev, "failed to power down lanes: %d\n", err); in tegra_sor_dp_link_configure()
936 /* power up and pre-charge lanes */ in tegra_sor_dp_link_configure()
939 dev_err(sor->dev, "failed to power up %u lane%s: %d\n", in tegra_sor_dp_link_configure()
994 return -ETIMEDOUT; in tegra_sor_setup_pwm()
1024 return -ETIMEDOUT; in tegra_sor_attach()
1044 return -ETIMEDOUT; in tegra_sor_wakeup()
1065 return -ETIMEDOUT; in tegra_sor_power_up()
1089 const u64 f = params->precision; in tegra_sor_compute_params()
1092 active_sym = params->ratio * tu_size; in tegra_sor_compute_params()
1094 frac = active_sym - active_count; in tegra_sor_compute_params()
1099 frac = f - frac; in tegra_sor_compute_params()
1122 approx = active_count + (active_frac * (f - 1)) * f; in tegra_sor_compute_params()
1134 error = div_s64(active_sym - approx, tu_size); in tegra_sor_compute_params()
1135 error *= params->num_clocks; in tegra_sor_compute_params()
1137 if (error <= 0 && abs(error) < params->error) { in tegra_sor_compute_params()
1138 params->active_count = div_u64(active_count, f); in tegra_sor_compute_params()
1139 params->active_polarity = active_polarity; in tegra_sor_compute_params()
1140 params->active_frac = active_frac; in tegra_sor_compute_params()
1141 params->error = abs(error); in tegra_sor_compute_params()
1142 params->tu_size = tu_size; in tegra_sor_compute_params()
1156 const u64 f = 100000, link_rate = link->rate * 1000; in tegra_sor_compute_config()
1157 const u64 pclk = (u64)mode->clock * 1000; in tegra_sor_compute_config()
1163 if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel) in tegra_sor_compute_config()
1164 return -EINVAL; in tegra_sor_compute_config()
1166 input = pclk * config->bits_per_pixel; in tegra_sor_compute_config()
1167 output = link_rate * 8 * link->lanes; in tegra_sor_compute_config()
1170 return -ERANGE; in tegra_sor_compute_config()
1174 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); in tegra_sor_compute_config()
1179 for (i = params.tu_size; i >= 32; i--) in tegra_sor_compute_config()
1184 config->active_polarity = 0; in tegra_sor_compute_config()
1185 config->active_count = params.active_count; in tegra_sor_compute_config()
1188 config->active_count--; in tegra_sor_compute_config()
1190 config->tu_size = params.tu_size; in tegra_sor_compute_config()
1191 config->active_frac = 1; in tegra_sor_compute_config()
1193 config->active_polarity = params.active_polarity; in tegra_sor_compute_config()
1194 config->active_count = params.active_count; in tegra_sor_compute_config()
1195 config->active_frac = params.active_frac; in tegra_sor_compute_config()
1196 config->tu_size = params.tu_size; in tegra_sor_compute_config()
1199 dev_dbg(sor->dev, in tegra_sor_compute_config()
1201 config->active_polarity, config->active_count, in tegra_sor_compute_config()
1202 config->tu_size, config->active_frac); in tegra_sor_compute_config()
1204 watermark = params.ratio * config->tu_size * (f - params.ratio); in tegra_sor_compute_config()
1208 config->watermark = watermark + (config->bits_per_pixel / 8) + 2; in tegra_sor_compute_config()
1209 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * in tegra_sor_compute_config()
1210 (link->lanes * 8); in tegra_sor_compute_config()
1212 if (config->watermark > 30) { in tegra_sor_compute_config()
1213 config->watermark = 30; in tegra_sor_compute_config()
1214 dev_err(sor->dev, in tegra_sor_compute_config()
1216 config->watermark); in tegra_sor_compute_config()
1217 } else if (config->watermark > num_syms_per_line) { in tegra_sor_compute_config()
1218 config->watermark = num_syms_per_line; in tegra_sor_compute_config()
1219 dev_err(sor->dev, "watermark too high, forcing to %u\n", in tegra_sor_compute_config()
1220 config->watermark); in tegra_sor_compute_config()
1224 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; in tegra_sor_compute_config()
1225 config->hblank_symbols = div_u64(num, pclk); in tegra_sor_compute_config()
1227 if (link->caps.enhanced_framing) in tegra_sor_compute_config()
1228 config->hblank_symbols -= 3; in tegra_sor_compute_config()
1230 config->hblank_symbols -= 12 / link->lanes; in tegra_sor_compute_config()
1233 num = (mode->hdisplay - 25) * link_rate; in tegra_sor_compute_config()
1234 config->vblank_symbols = div_u64(num, pclk); in tegra_sor_compute_config()
1235 config->vblank_symbols -= 36 / link->lanes + 4; in tegra_sor_compute_config()
1237 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, in tegra_sor_compute_config()
1238 config->vblank_symbols); in tegra_sor_compute_config()
1250 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); in tegra_sor_apply_config()
1255 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); in tegra_sor_apply_config()
1258 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); in tegra_sor_apply_config()
1261 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); in tegra_sor_apply_config()
1263 if (config->active_polarity) in tegra_sor_apply_config()
1274 value |= config->hblank_symbols & 0xffff; in tegra_sor_apply_config()
1279 value |= config->vblank_symbols & 0xffff; in tegra_sor_apply_config()
1287 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); in tegra_sor_mode_set()
1297 SOR_STATE_ASY_OWNER(dc->pipe + 1); in tegra_sor_mode_set()
1299 if (mode->flags & DRM_MODE_FLAG_PHSYNC) in tegra_sor_mode_set()
1302 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in tegra_sor_mode_set()
1305 if (mode->flags & DRM_MODE_FLAG_PVSYNC) in tegra_sor_mode_set()
1308 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in tegra_sor_mode_set()
1311 switch (state->bpc) { in tegra_sor_mode_set()
1344 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); in tegra_sor_mode_set()
1345 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); in tegra_sor_mode_set()
1347 /* sync end = sync width - 1 */ in tegra_sor_mode_set()
1348 vse = mode->vsync_end - mode->vsync_start - 1; in tegra_sor_mode_set()
1349 hse = mode->hsync_end - mode->hsync_start - 1; in tegra_sor_mode_set()
1352 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); in tegra_sor_mode_set()
1355 vbe = vse + (mode->vtotal - mode->vsync_end); in tegra_sor_mode_set()
1356 hbe = hse + (mode->htotal - mode->hsync_end); in tegra_sor_mode_set()
1359 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); in tegra_sor_mode_set()
1362 vbs = vbe + mode->vdisplay; in tegra_sor_mode_set()
1363 hbs = hbe + mode->hdisplay; in tegra_sor_mode_set()
1366 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); in tegra_sor_mode_set()
1369 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); in tegra_sor_mode_set()
1391 return -ETIMEDOUT; in tegra_sor_detach()
1416 return -ETIMEDOUT; in tegra_sor_detach()
1442 return -ETIMEDOUT; in tegra_sor_power_down()
1445 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_power_down()
1447 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_power_down()
1451 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1453 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1457 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1459 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1461 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1464 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1485 return -ETIMEDOUT; in tegra_sor_crc_wait()
1490 struct drm_info_node *node = s->private; in tegra_sor_show_crc()
1491 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_crc()
1492 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_crc()
1493 struct drm_device *drm = node->minor->dev; in tegra_sor_show_crc()
1499 if (!crtc || !crtc->state->active) { in tegra_sor_show_crc()
1500 err = -EBUSY; in tegra_sor_show_crc()
1652 struct drm_info_node *node = s->private; in tegra_sor_show_regs()
1653 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_regs()
1654 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_regs()
1655 struct drm_device *drm = node->minor->dev; in tegra_sor_show_regs()
1661 if (!crtc || !crtc->state->active) { in tegra_sor_show_regs()
1662 err = -EBUSY; in tegra_sor_show_regs()
1669 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name, in tegra_sor_show_regs()
1687 struct drm_minor *minor = connector->dev->primary; in tegra_sor_late_register()
1688 struct dentry *root = connector->debugfs_entry; in tegra_sor_late_register()
1691 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_sor_late_register()
1693 if (!sor->debugfs_files) in tegra_sor_late_register()
1694 return -ENOMEM; in tegra_sor_late_register()
1697 sor->debugfs_files[i].data = sor; in tegra_sor_late_register()
1699 drm_debugfs_create_files(sor->debugfs_files, count, root, minor); in tegra_sor_late_register()
1710 drm_debugfs_remove_files(sor->debugfs_files, count, in tegra_sor_early_unregister()
1711 connector->dev->primary); in tegra_sor_early_unregister()
1712 kfree(sor->debugfs_files); in tegra_sor_early_unregister()
1713 sor->debugfs_files = NULL; in tegra_sor_early_unregister()
1724 if (connector->state) { in tegra_sor_connector_reset()
1725 __drm_atomic_helper_connector_destroy_state(connector->state); in tegra_sor_connector_reset()
1726 kfree(connector->state); in tegra_sor_connector_reset()
1729 __drm_atomic_helper_connector_reset(connector, &state->base); in tegra_sor_connector_reset()
1738 if (sor->aux) in tegra_sor_connector_detect()
1739 return drm_dp_aux_detect(sor->aux); in tegra_sor_connector_detect()
1747 struct tegra_sor_state *state = to_sor_state(connector->state); in tegra_sor_connector_duplicate_state()
1754 __drm_atomic_helper_connector_duplicate_state(connector, ©->base); in tegra_sor_connector_duplicate_state()
1756 return ©->base; in tegra_sor_connector_duplicate_state()
1776 if (sor->aux) in tegra_sor_connector_get_modes()
1777 drm_dp_aux_enable(sor->aux); in tegra_sor_connector_get_modes()
1781 if (sor->aux) in tegra_sor_connector_get_modes()
1782 drm_dp_aux_disable(sor->aux); in tegra_sor_connector_get_modes()
1806 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); in tegra_sor_encoder_atomic_check()
1807 unsigned long pclk = crtc_state->mode.clock * 1000; in tegra_sor_encoder_atomic_check()
1812 info = &output->connector.display_info; in tegra_sor_encoder_atomic_check()
1819 state->link_speed = 20; in tegra_sor_encoder_atomic_check()
1820 state->pclk = pclk / 2; in tegra_sor_encoder_atomic_check()
1822 state->link_speed = 10; in tegra_sor_encoder_atomic_check()
1823 state->pclk = pclk; in tegra_sor_encoder_atomic_check()
1826 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, in tegra_sor_encoder_atomic_check()
1829 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); in tegra_sor_encoder_atomic_check()
1833 switch (info->bpc) { in tegra_sor_encoder_atomic_check()
1836 state->bpc = info->bpc; in tegra_sor_encoder_atomic_check()
1840 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc); in tegra_sor_encoder_atomic_check()
1841 state->bpc = 8; in tegra_sor_encoder_atomic_check()
1853 for (i = size; i > 0; i--) in tegra_sor_hdmi_subpack()
1854 value = (value << 8) | ptr[i - 1]; in tegra_sor_hdmi_subpack()
1881 dev_err(sor->dev, "unsupported infoframe type: %02x\n", in tegra_sor_hdmi_write_infopack()
1894 * - subpack_low: bytes 0 - 3 in tegra_sor_hdmi_write_infopack()
1895 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) in tegra_sor_hdmi_write_infopack()
1898 size_t rem = size - i, num = min_t(size_t, rem, 4); in tegra_sor_hdmi_write_infopack()
1903 num = min_t(size_t, rem - num, 3); in tegra_sor_hdmi_write_infopack()
1927 &sor->output.connector, mode); in tegra_sor_hdmi_setup_avi_infoframe()
1929 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
1935 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
1952 size_t length = drm_eld_size(sor->output.connector.eld), i; in tegra_sor_write_eld()
1955 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i], in tegra_sor_write_eld()
2005 if (sor->format.channels != 2) in tegra_sor_audio_enable()
2027 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err); in tegra_sor_hdmi_enable_audio_infoframe()
2031 frame.channels = sor->format.channels; in tegra_sor_hdmi_enable_audio_infoframe()
2035 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err); in tegra_sor_hdmi_enable_audio_infoframe()
2074 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2087 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2091 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2095 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2125 for (i = 0; i < sor->num_settings; i++) in tegra_sor_hdmi_find_settings()
2126 if (frequency <= sor->settings[i].frequency) in tegra_sor_hdmi_find_settings()
2127 return &sor->settings[i]; in tegra_sor_hdmi_find_settings()
2144 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, false); in tegra_sor_hdmi_scdc_disable()
2145 drm_scdc_set_scrambling(&sor->output.connector, false); in tegra_sor_hdmi_scdc_disable()
2152 if (sor->scdc_enabled) { in tegra_sor_hdmi_scdc_stop()
2153 cancel_delayed_work_sync(&sor->scdc); in tegra_sor_hdmi_scdc_stop()
2170 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, true); in tegra_sor_hdmi_scdc_enable()
2171 drm_scdc_set_scrambling(&sor->output.connector, true); in tegra_sor_hdmi_scdc_enable()
2180 if (!drm_scdc_get_scrambling_status(&sor->output.connector)) { in tegra_sor_hdmi_scdc_work()
2185 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); in tegra_sor_hdmi_scdc_work()
2190 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; in tegra_sor_hdmi_scdc_start()
2193 mode = &sor->output.encoder.crtc->state->adjusted_mode; in tegra_sor_hdmi_scdc_start()
2195 if (mode->clock >= 340000 && scdc->supported) { in tegra_sor_hdmi_scdc_start()
2196 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); in tegra_sor_hdmi_scdc_start()
2198 sor->scdc_enabled = true; in tegra_sor_hdmi_scdc_start()
2205 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_sor_hdmi_disable()
2215 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_hdmi_disable()
2220 /* disable display to SOR clock */ in tegra_sor_hdmi_disable()
2223 if (!sor->soc->has_nvdisplay) in tegra_sor_hdmi_disable()
2226 value &= ~SOR_ENABLE(sor->index); in tegra_sor_hdmi_disable()
2234 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_hdmi_disable()
2236 err = tegra_io_pad_power_disable(sor->pad); in tegra_sor_hdmi_disable()
2238 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); in tegra_sor_hdmi_disable()
2240 host1x_client_suspend(&sor->client); in tegra_sor_hdmi_disable()
2247 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_sor_hdmi_enable()
2257 state = to_sor_state(output->connector.state); in tegra_sor_hdmi_enable()
2258 mode = &encoder->crtc->state->adjusted_mode; in tegra_sor_hdmi_enable()
2259 pclk = mode->clock * 1000; in tegra_sor_hdmi_enable()
2261 err = host1x_client_resume(&sor->client); in tegra_sor_hdmi_enable()
2263 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_hdmi_enable()
2268 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_hdmi_enable()
2270 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_hdmi_enable()
2274 div = clk_get_rate(sor->clk) / 1000000 * 4; in tegra_sor_hdmi_enable()
2276 err = tegra_io_pad_power_enable(sor->pad); in tegra_sor_hdmi_enable()
2278 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); in tegra_sor_hdmi_enable()
2282 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2284 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2288 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2290 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2292 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2295 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2297 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2299 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2303 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2306 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2310 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2313 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2339 if (mode->clock < 340000) { in tegra_sor_hdmi_enable()
2374 if (!sor->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2382 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | in tegra_sor_hdmi_enable()
2390 * do this because Tegra186 and later don't support clk_set_parent() in tegra_sor_hdmi_enable()
2395 err = clk_set_parent(sor->clk_pad, sor->clk_dp); in tegra_sor_hdmi_enable()
2397 dev_err(sor->dev, "failed to select pad parent clock: %d\n", in tegra_sor_hdmi_enable()
2404 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); in tegra_sor_hdmi_enable()
2406 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", in tegra_sor_hdmi_enable()
2412 err = clk_set_parent(sor->clk, sor->clk_parent); in tegra_sor_hdmi_enable()
2414 dev_err(sor->dev, "failed to select output parent clock: %d\n", in tegra_sor_hdmi_enable()
2420 rate = clk_get_rate(sor->clk_parent); in tegra_sor_hdmi_enable()
2422 if (mode->clock >= 340000) in tegra_sor_hdmi_enable()
2427 clk_set_rate(sor->clk, rate); in tegra_sor_hdmi_enable()
2429 if (!sor->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2430 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); in tegra_sor_hdmi_enable()
2433 if (mode->clock < 75000) in tegra_sor_hdmi_enable()
2439 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32; in tegra_sor_hdmi_enable()
2445 if (!dc->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2448 (mode->hsync_end - mode->hsync_start) + in tegra_sor_hdmi_enable()
2449 (mode->htotal - mode->hsync_end) - 10; in tegra_sor_hdmi_enable()
2466 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_enable()
2478 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2480 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2483 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); in tegra_sor_hdmi_enable()
2485 dev_err(sor->dev, "no settings for pixel clock %d Hz\n", in tegra_sor_hdmi_enable()
2486 mode->clock * 1000); in tegra_sor_hdmi_enable()
2490 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2494 value |= SOR_PLL0_ICHPMP(settings->ichpmp); in tegra_sor_hdmi_enable()
2495 value |= SOR_PLL0_FILTER(settings->filter); in tegra_sor_hdmi_enable()
2496 value |= SOR_PLL0_VCOCAP(settings->vcocap); in tegra_sor_hdmi_enable()
2497 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2500 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2503 value |= SOR_PLL1_LOADADJ(settings->loadadj); in tegra_sor_hdmi_enable()
2504 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); in tegra_sor_hdmi_enable()
2506 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2508 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2513 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); in tegra_sor_hdmi_enable()
2514 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); in tegra_sor_hdmi_enable()
2515 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); in tegra_sor_hdmi_enable()
2516 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); in tegra_sor_hdmi_enable()
2517 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2519 value = settings->drive_current[3] << 24 | in tegra_sor_hdmi_enable()
2520 settings->drive_current[2] << 16 | in tegra_sor_hdmi_enable()
2521 settings->drive_current[1] << 8 | in tegra_sor_hdmi_enable()
2522 settings->drive_current[0] << 0; in tegra_sor_hdmi_enable()
2525 value = settings->preemphasis[3] << 24 | in tegra_sor_hdmi_enable()
2526 settings->preemphasis[2] << 16 | in tegra_sor_hdmi_enable()
2527 settings->preemphasis[1] << 8 | in tegra_sor_hdmi_enable()
2528 settings->preemphasis[0] << 0; in tegra_sor_hdmi_enable()
2531 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2534 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); in tegra_sor_hdmi_enable()
2535 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2537 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2539 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); in tegra_sor_hdmi_enable()
2540 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2543 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2545 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2547 if (!dc->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2548 /* miscellaneous display controller settings */ in tegra_sor_hdmi_enable()
2557 switch (state->bpc) { in tegra_sor_hdmi_enable()
2575 WARN(1, "%u bits-per-color not supported\n", state->bpc); in tegra_sor_hdmi_enable()
2582 /* XXX set display head owner */ in tegra_sor_hdmi_enable()
2585 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); in tegra_sor_hdmi_enable()
2590 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_hdmi_enable()
2593 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2596 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2599 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2602 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2615 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_hdmi_enable()
2617 /* enable display to SOR clock and generate HDMI preamble */ in tegra_sor_hdmi_enable()
2620 if (!sor->soc->has_nvdisplay) in tegra_sor_hdmi_enable()
2623 value |= SOR_ENABLE(sor->index); in tegra_sor_hdmi_enable()
2627 if (dc->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2628 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2631 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2638 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); in tegra_sor_hdmi_enable()
2653 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_sor_dp_disable()
2658 if (output->panel) in tegra_sor_dp_disable()
2659 drm_panel_disable(output->panel); in tegra_sor_dp_disable()
2665 if (output->connector.status != connector_status_disconnected) { in tegra_sor_dp_disable()
2666 err = drm_dp_link_power_down(sor->aux, &sor->link); in tegra_sor_dp_disable()
2668 dev_err(sor->dev, "failed to power down link: %d\n", in tegra_sor_dp_disable()
2674 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_dp_disable()
2680 value &= ~SOR_ENABLE(sor->index); in tegra_sor_dp_disable()
2692 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_dp_disable()
2694 dev_err(sor->dev, "failed to set safe clock: %d\n", err); in tegra_sor_dp_disable()
2698 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_dp_disable()
2700 err = tegra_io_pad_power_disable(sor->pad); in tegra_sor_dp_disable()
2702 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); in tegra_sor_dp_disable()
2704 err = drm_dp_aux_disable(sor->aux); in tegra_sor_dp_disable()
2706 dev_err(sor->dev, "failed disable DPAUX: %d\n", err); in tegra_sor_dp_disable()
2708 if (output->panel) in tegra_sor_dp_disable()
2709 drm_panel_unprepare(output->panel); in tegra_sor_dp_disable()
2711 host1x_client_suspend(&sor->client); in tegra_sor_dp_disable()
2717 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_sor_dp_enable()
2727 state = to_sor_state(output->connector.state); in tegra_sor_dp_enable()
2728 mode = &encoder->crtc->state->adjusted_mode; in tegra_sor_dp_enable()
2729 info = &output->connector.display_info; in tegra_sor_dp_enable()
2731 err = host1x_client_resume(&sor->client); in tegra_sor_dp_enable()
2733 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_dp_enable()
2738 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_dp_enable()
2740 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_dp_enable()
2742 err = tegra_io_pad_power_enable(sor->pad); in tegra_sor_dp_enable()
2744 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err); in tegra_sor_dp_enable()
2748 err = drm_dp_aux_enable(sor->aux); in tegra_sor_dp_enable()
2750 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err); in tegra_sor_dp_enable()
2752 err = drm_dp_link_probe(sor->aux, &sor->link); in tegra_sor_dp_enable()
2754 dev_err(sor->dev, "failed to probe DP link: %d\n", err); in tegra_sor_dp_enable()
2758 err = drm_dp_link_choose(&sor->link, mode, info); in tegra_sor_dp_enable()
2760 dev_err(sor->dev, "failed to choose link: %d\n", err); in tegra_sor_dp_enable()
2762 if (output->panel) in tegra_sor_dp_enable()
2763 drm_panel_prepare(output->panel); in tegra_sor_dp_enable()
2765 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2767 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2771 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2773 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2775 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2777 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2779 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2782 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2786 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2789 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2794 if (output->panel) in tegra_sor_dp_enable()
2805 if (output->panel) in tegra_sor_dp_enable()
2816 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2822 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2826 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | in tegra_sor_dp_enable()
2834 * do this because Tegra186 and later don't support clk_set_parent() in tegra_sor_dp_enable()
2839 err = clk_set_parent(sor->clk_pad, sor->clk_parent); in tegra_sor_dp_enable()
2841 dev_err(sor->dev, "failed to select pad parent clock: %d\n", in tegra_sor_dp_enable()
2848 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); in tegra_sor_dp_enable()
2850 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", in tegra_sor_dp_enable()
2856 err = clk_set_parent(sor->clk, sor->clk_parent); in tegra_sor_dp_enable()
2858 dev_err(sor->dev, "failed to select output parent clock: %d\n", in tegra_sor_dp_enable()
2863 /* use DP-A protocol */ in tegra_sor_dp_enable()
2876 err = drm_dp_link_train(&sor->link); in tegra_sor_dp_enable()
2878 dev_err(sor->dev, "link training failed: %d\n", err); in tegra_sor_dp_enable()
2880 dev_dbg(sor->dev, "link training succeeded\n"); in tegra_sor_dp_enable()
2882 err = drm_dp_link_power_up(sor->aux, &sor->link); in tegra_sor_dp_enable()
2884 dev_err(sor->dev, "failed to power up DP link: %d\n", err); in tegra_sor_dp_enable()
2888 config.bits_per_pixel = state->bpc * 3; in tegra_sor_dp_enable()
2890 err = tegra_sor_compute_config(sor, mode, &config, &sor->link); in tegra_sor_dp_enable()
2892 dev_err(sor->dev, "failed to compute configuration: %d\n", err); in tegra_sor_dp_enable()
2897 if (output->panel) { in tegra_sor_dp_enable()
2906 dev_err(sor->dev, "failed to setup PWM: %d\n", err); in tegra_sor_dp_enable()
2913 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_dp_enable()
2918 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_dp_enable()
2921 value |= SOR_ENABLE(sor->index); in tegra_sor_dp_enable()
2928 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); in tegra_sor_dp_enable()
2930 if (output->panel) in tegra_sor_dp_enable()
2931 drm_panel_enable(output->panel); in tegra_sor_dp_enable()
2955 return devm_add_action_or_reset(sor->dev, tegra_sor_disable_regulator, reg); in tegra_sor_enable_regulator()
2962 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); in tegra_sor_hdmi_probe()
2963 if (IS_ERR(sor->avdd_io_supply)) in tegra_sor_hdmi_probe()
2964 return dev_err_probe(sor->dev, PTR_ERR(sor->avdd_io_supply), in tegra_sor_hdmi_probe()
2967 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply); in tegra_sor_hdmi_probe()
2969 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", in tegra_sor_hdmi_probe()
2974 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); in tegra_sor_hdmi_probe()
2975 if (IS_ERR(sor->vdd_pll_supply)) in tegra_sor_hdmi_probe()
2976 return dev_err_probe(sor->dev, PTR_ERR(sor->vdd_pll_supply), in tegra_sor_hdmi_probe()
2979 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply); in tegra_sor_hdmi_probe()
2981 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", in tegra_sor_hdmi_probe()
2986 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); in tegra_sor_hdmi_probe()
2987 if (IS_ERR(sor->hdmi_supply)) in tegra_sor_hdmi_probe()
2988 return dev_err_probe(sor->dev, PTR_ERR(sor->hdmi_supply), in tegra_sor_hdmi_probe()
2991 err = tegra_sor_enable_regulator(sor, sor->hdmi_supply); in tegra_sor_hdmi_probe()
2993 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); in tegra_sor_hdmi_probe()
2997 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); in tegra_sor_hdmi_probe()
3013 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); in tegra_sor_dp_probe()
3014 if (IS_ERR(sor->avdd_io_supply)) in tegra_sor_dp_probe()
3015 return PTR_ERR(sor->avdd_io_supply); in tegra_sor_dp_probe()
3017 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply); in tegra_sor_dp_probe()
3021 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); in tegra_sor_dp_probe()
3022 if (IS_ERR(sor->vdd_pll_supply)) in tegra_sor_dp_probe()
3023 return PTR_ERR(sor->vdd_pll_supply); in tegra_sor_dp_probe()
3025 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply); in tegra_sor_dp_probe()
3039 struct drm_device *drm = dev_get_drvdata(client->host); in tegra_sor_init()
3046 if (!sor->aux) { in tegra_sor_init()
3047 if (sor->ops == &tegra_sor_hdmi_ops) { in tegra_sor_init()
3051 } else if (sor->soc->supports_lvds) { in tegra_sor_init()
3056 if (sor->output.panel) { in tegra_sor_init()
3066 sor->link.ops = &tegra_sor_dp_link_ops; in tegra_sor_init()
3067 sor->link.aux = sor->aux; in tegra_sor_init()
3070 sor->output.dev = sor->dev; in tegra_sor_init()
3072 drm_connector_init_with_ddc(drm, &sor->output.connector, in tegra_sor_init()
3075 sor->output.ddc); in tegra_sor_init()
3076 drm_connector_helper_add(&sor->output.connector, in tegra_sor_init()
3078 sor->output.connector.dpms = DRM_MODE_DPMS_OFF; in tegra_sor_init()
3080 drm_simple_encoder_init(drm, &sor->output.encoder, encoder); in tegra_sor_init()
3081 drm_encoder_helper_add(&sor->output.encoder, helpers); in tegra_sor_init()
3083 drm_connector_attach_encoder(&sor->output.connector, in tegra_sor_init()
3084 &sor->output.encoder); in tegra_sor_init()
3085 drm_connector_register(&sor->output.connector); in tegra_sor_init()
3087 err = tegra_output_init(drm, &sor->output); in tegra_sor_init()
3089 dev_err(client->dev, "failed to initialize output: %d\n", err); in tegra_sor_init()
3093 tegra_output_find_possible_crtcs(&sor->output, drm); in tegra_sor_init()
3095 if (sor->aux) { in tegra_sor_init()
3096 err = drm_dp_aux_attach(sor->aux, &sor->output); in tegra_sor_init()
3098 dev_err(sor->dev, "failed to attach DP: %d\n", err); in tegra_sor_init()
3104 * XXX: Remove this reset once proper hand-over from firmware to in tegra_sor_init()
3107 if (sor->rst) { in tegra_sor_init()
3108 err = pm_runtime_resume_and_get(sor->dev); in tegra_sor_init()
3110 dev_err(sor->dev, "failed to get runtime PM: %d\n", err); in tegra_sor_init()
3114 err = reset_control_acquire(sor->rst); in tegra_sor_init()
3116 dev_err(sor->dev, "failed to acquire SOR reset: %d\n", in tegra_sor_init()
3121 err = reset_control_assert(sor->rst); in tegra_sor_init()
3123 dev_err(sor->dev, "failed to assert SOR reset: %d\n", in tegra_sor_init()
3129 err = clk_prepare_enable(sor->clk); in tegra_sor_init()
3131 dev_err(sor->dev, "failed to enable clock: %d\n", err); in tegra_sor_init()
3137 if (sor->rst) { in tegra_sor_init()
3138 err = reset_control_deassert(sor->rst); in tegra_sor_init()
3140 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", in tegra_sor_init()
3142 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3146 reset_control_release(sor->rst); in tegra_sor_init()
3147 pm_runtime_put(sor->dev); in tegra_sor_init()
3150 err = clk_prepare_enable(sor->clk_safe); in tegra_sor_init()
3152 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3156 err = clk_prepare_enable(sor->clk_dp); in tegra_sor_init()
3158 clk_disable_unprepare(sor->clk_safe); in tegra_sor_init()
3159 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3166 if (sor->rst) in tegra_sor_init()
3167 pm_runtime_put(sor->dev); in tegra_sor_init()
3177 tegra_output_exit(&sor->output); in tegra_sor_exit()
3179 if (sor->aux) { in tegra_sor_exit()
3180 err = drm_dp_aux_detach(sor->aux); in tegra_sor_exit()
3182 dev_err(sor->dev, "failed to detach DP: %d\n", err); in tegra_sor_exit()
3187 clk_disable_unprepare(sor->clk_safe); in tegra_sor_exit()
3188 clk_disable_unprepare(sor->clk_dp); in tegra_sor_exit()
3189 clk_disable_unprepare(sor->clk); in tegra_sor_exit()
3197 struct device *dev = client->dev; in tegra_sor_runtime_suspend()
3200 if (sor->rst) { in tegra_sor_runtime_suspend()
3201 err = reset_control_assert(sor->rst); in tegra_sor_runtime_suspend()
3207 reset_control_release(sor->rst); in tegra_sor_runtime_suspend()
3212 clk_disable_unprepare(sor->clk); in tegra_sor_runtime_suspend()
3221 struct device *dev = client->dev; in tegra_sor_runtime_resume()
3230 err = clk_prepare_enable(sor->clk); in tegra_sor_runtime_resume()
3238 if (sor->rst) { in tegra_sor_runtime_resume()
3239 err = reset_control_acquire(sor->rst); in tegra_sor_runtime_resume()
3245 err = reset_control_deassert(sor->rst); in tegra_sor_runtime_resume()
3255 reset_control_release(sor->rst); in tegra_sor_runtime_resume()
3257 clk_disable_unprepare(sor->clk); in tegra_sor_runtime_resume()
3627 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3628 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3629 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3630 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3631 { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3632 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3639 struct device_node *np = sor->dev->of_node; in tegra_sor_parse_dt()
3645 if (sor->soc->has_nvdisplay) { in tegra_sor_parse_dt()
3650 sor->index = value; in tegra_sor_parse_dt()
3656 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; in tegra_sor_parse_dt()
3658 if (!sor->soc->supports_audio) in tegra_sor_parse_dt()
3659 sor->index = 0; in tegra_sor_parse_dt()
3661 sor->index = 1; in tegra_sor_parse_dt()
3664 err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5); in tegra_sor_parse_dt()
3666 /* fall back to default per-SoC XBAR configuration */ in tegra_sor_parse_dt()
3668 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i]; in tegra_sor_parse_dt()
3672 sor->xbar_cfg[i] = xbar_cfg[i]; in tegra_sor_parse_dt()
3694 tegra_hda_parse_format(format, &sor->format); in tegra_sor_irq()
3696 if (sor->ops->audio_enable) in tegra_sor_irq()
3697 sor->ops->audio_enable(sor); in tegra_sor_irq()
3699 if (sor->ops->audio_disable) in tegra_sor_irq()
3700 sor->ops->audio_disable(sor); in tegra_sor_irq()
3713 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); in tegra_sor_probe()
3715 return -ENOMEM; in tegra_sor_probe()
3717 sor->soc = of_device_get_match_data(&pdev->dev); in tegra_sor_probe()
3718 sor->output.dev = sor->dev = &pdev->dev; in tegra_sor_probe()
3720 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, in tegra_sor_probe()
3721 sor->soc->num_settings * in tegra_sor_probe()
3722 sizeof(*sor->settings), in tegra_sor_probe()
3724 if (!sor->settings) in tegra_sor_probe()
3725 return -ENOMEM; in tegra_sor_probe()
3727 sor->num_settings = sor->soc->num_settings; in tegra_sor_probe()
3729 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); in tegra_sor_probe()
3731 sor->aux = drm_dp_aux_find_by_of_node(np); in tegra_sor_probe()
3734 if (!sor->aux) in tegra_sor_probe()
3735 return -EPROBE_DEFER; in tegra_sor_probe()
3737 if (get_device(sor->aux->dev)) in tegra_sor_probe()
3738 sor->output.ddc = &sor->aux->ddc; in tegra_sor_probe()
3741 if (!sor->aux) { in tegra_sor_probe()
3742 if (sor->soc->supports_hdmi) { in tegra_sor_probe()
3743 sor->ops = &tegra_sor_hdmi_ops; in tegra_sor_probe()
3744 sor->pad = TEGRA_IO_PAD_HDMI; in tegra_sor_probe()
3745 } else if (sor->soc->supports_lvds) { in tegra_sor_probe()
3746 dev_err(&pdev->dev, "LVDS not supported yet\n"); in tegra_sor_probe()
3747 return -ENODEV; in tegra_sor_probe()
3749 dev_err(&pdev->dev, "unknown (non-DP) support\n"); in tegra_sor_probe()
3750 return -ENODEV; in tegra_sor_probe()
3753 np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0); in tegra_sor_probe()
3760 sor->ops = &tegra_sor_dp_ops; in tegra_sor_probe()
3761 sor->pad = TEGRA_IO_PAD_LVDS; in tegra_sor_probe()
3768 err = tegra_output_probe(&sor->output); in tegra_sor_probe()
3770 dev_err_probe(&pdev->dev, err, "failed to probe output\n"); in tegra_sor_probe()
3774 if (sor->ops && sor->ops->probe) { in tegra_sor_probe()
3775 err = sor->ops->probe(sor); in tegra_sor_probe()
3777 dev_err(&pdev->dev, "failed to probe %s: %d\n", in tegra_sor_probe()
3778 sor->ops->name, err); in tegra_sor_probe()
3783 sor->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_sor_probe()
3784 if (IS_ERR(sor->regs)) { in tegra_sor_probe()
3785 err = PTR_ERR(sor->regs); in tegra_sor_probe()
3793 sor->irq = err; in tegra_sor_probe()
3795 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0, in tegra_sor_probe()
3796 dev_name(sor->dev), sor); in tegra_sor_probe()
3798 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); in tegra_sor_probe()
3802 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor"); in tegra_sor_probe()
3803 if (IS_ERR(sor->rst)) { in tegra_sor_probe()
3804 err = PTR_ERR(sor->rst); in tegra_sor_probe()
3806 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) { in tegra_sor_probe()
3807 dev_err(&pdev->dev, "failed to get reset control: %d\n", in tegra_sor_probe()
3818 sor->rst = NULL; in tegra_sor_probe()
3821 sor->clk = devm_clk_get(&pdev->dev, NULL); in tegra_sor_probe()
3822 if (IS_ERR(sor->clk)) { in tegra_sor_probe()
3823 err = PTR_ERR(sor->clk); in tegra_sor_probe()
3824 dev_err(&pdev->dev, "failed to get module clock: %d\n", err); in tegra_sor_probe()
3828 if (sor->soc->supports_hdmi || sor->soc->supports_dp) { in tegra_sor_probe()
3829 struct device_node *np = pdev->dev.of_node; in tegra_sor_probe()
3837 if (of_property_match_string(np, "clock-names", "out") < 0) in tegra_sor_probe()
3842 sor->clk_out = devm_clk_get(&pdev->dev, name); in tegra_sor_probe()
3843 if (IS_ERR(sor->clk_out)) { in tegra_sor_probe()
3844 err = PTR_ERR(sor->clk_out); in tegra_sor_probe()
3845 dev_err(sor->dev, "failed to get %s clock: %d\n", in tegra_sor_probe()
3851 sor->clk_out = sor->clk; in tegra_sor_probe()
3854 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); in tegra_sor_probe()
3855 if (IS_ERR(sor->clk_parent)) { in tegra_sor_probe()
3856 err = PTR_ERR(sor->clk_parent); in tegra_sor_probe()
3857 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err); in tegra_sor_probe()
3861 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); in tegra_sor_probe()
3862 if (IS_ERR(sor->clk_safe)) { in tegra_sor_probe()
3863 err = PTR_ERR(sor->clk_safe); in tegra_sor_probe()
3864 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err); in tegra_sor_probe()
3868 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); in tegra_sor_probe()
3869 if (IS_ERR(sor->clk_dp)) { in tegra_sor_probe()
3870 err = PTR_ERR(sor->clk_dp); in tegra_sor_probe()
3871 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err); in tegra_sor_probe()
3876 * Starting with Tegra186, the BPMP provides an implementation for in tegra_sor_probe()
3879 sor->clk_pad = devm_clk_get(&pdev->dev, "pad"); in tegra_sor_probe()
3880 if (IS_ERR(sor->clk_pad)) { in tegra_sor_probe()
3881 if (sor->clk_pad != ERR_PTR(-ENOENT)) { in tegra_sor_probe()
3882 err = PTR_ERR(sor->clk_pad); in tegra_sor_probe()
3891 sor->clk_pad = NULL; in tegra_sor_probe()
3896 * is sourced by one of the display PLLs. However, that doesn't work in tegra_sor_probe()
3899 err = clk_set_parent(sor->clk_out, sor->clk_safe); in tegra_sor_probe()
3901 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err); in tegra_sor_probe()
3906 pm_runtime_enable(&pdev->dev); in tegra_sor_probe()
3908 host1x_client_init(&sor->client); in tegra_sor_probe()
3909 sor->client.ops = &sor_client_ops; in tegra_sor_probe()
3910 sor->client.dev = &pdev->dev; in tegra_sor_probe()
3916 if (!sor->clk_pad) { in tegra_sor_probe()
3919 name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout", in tegra_sor_probe()
3920 sor->index); in tegra_sor_probe()
3922 err = -ENOMEM; in tegra_sor_probe()
3926 err = host1x_client_resume(&sor->client); in tegra_sor_probe()
3928 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_probe()
3932 sor->clk_pad = tegra_clk_sor_pad_register(sor, name); in tegra_sor_probe()
3933 host1x_client_suspend(&sor->client); in tegra_sor_probe()
3936 if (IS_ERR(sor->clk_pad)) { in tegra_sor_probe()
3937 err = PTR_ERR(sor->clk_pad); in tegra_sor_probe()
3938 dev_err(sor->dev, "failed to register SOR pad clock: %d\n", in tegra_sor_probe()
3943 err = __host1x_client_register(&sor->client); in tegra_sor_probe()
3945 dev_err(&pdev->dev, "failed to register host1x client: %d\n", in tegra_sor_probe()
3953 host1x_client_exit(&sor->client); in tegra_sor_probe()
3954 pm_runtime_disable(&pdev->dev); in tegra_sor_probe()
3956 if (sor->aux) in tegra_sor_probe()
3957 sor->output.ddc = NULL; in tegra_sor_probe()
3959 tegra_output_remove(&sor->output); in tegra_sor_probe()
3961 if (sor->aux) in tegra_sor_probe()
3962 put_device(sor->aux->dev); in tegra_sor_probe()
3971 host1x_client_unregister(&sor->client); in tegra_sor_remove()
3973 pm_runtime_disable(&pdev->dev); in tegra_sor_remove()
3975 if (sor->aux) { in tegra_sor_remove()
3976 put_device(sor->aux->dev); in tegra_sor_remove()
3977 sor->output.ddc = NULL; in tegra_sor_remove()
3980 tegra_output_remove(&sor->output); in tegra_sor_remove()
3988 err = tegra_output_suspend(&sor->output); in tegra_sor_suspend()
3994 if (sor->hdmi_supply) { in tegra_sor_suspend()
3995 err = regulator_disable(sor->hdmi_supply); in tegra_sor_suspend()
3997 tegra_output_resume(&sor->output); in tegra_sor_suspend()
4010 if (sor->hdmi_supply) { in tegra_sor_resume()
4011 err = regulator_enable(sor->hdmi_supply); in tegra_sor_resume()
4016 err = tegra_output_resume(&sor->output); in tegra_sor_resume()
4020 if (sor->hdmi_supply) in tegra_sor_resume()
4021 regulator_disable(sor->hdmi_supply); in tegra_sor_resume()
4035 .name = "tegra-sor",