Lines Matching +full:dc +full:- +full:to +full:- +full:dc
1 // SPDX-License-Identifier: GPL-2.0-only
15 #include "dc.h"
19 struct tegra_dc *dc; member
81 static void tegra_dc_write_regs(struct tegra_dc *dc, in tegra_dc_write_regs() argument
88 tegra_dc_writel(dc, table[i].value, table[i].offset); in tegra_dc_write_regs()
96 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable)); in tegra_rgb_encoder_disable()
97 tegra_dc_commit(rgb->dc); in tegra_rgb_encoder_disable()
106 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable)); in tegra_rgb_encoder_enable()
109 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); in tegra_rgb_encoder_enable()
112 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1)); in tegra_rgb_encoder_enable()
115 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); in tegra_rgb_encoder_enable()
120 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL); in tegra_rgb_encoder_enable()
122 tegra_dc_commit(rgb->dc); in tegra_rgb_encoder_enable()
127 if (!rgb->pll_d2_out0) in tegra_rgb_pll_rate_change_allowed()
130 if (!clk_is_match(rgb->clk_parent, rgb->pll_d_out0) && in tegra_rgb_pll_rate_change_allowed()
131 !clk_is_match(rgb->clk_parent, rgb->pll_d2_out0)) in tegra_rgb_pll_rate_change_allowed()
143 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); in tegra_rgb_encoder_atomic_check() local
144 unsigned long pclk = crtc_state->mode.clock * 1000; in tegra_rgb_encoder_atomic_check()
150 * We may not want to change the frequency of the parent clock, since in tegra_rgb_encoder_atomic_check()
151 * it may be a parent for other peripherals. This is due to the fact in tegra_rgb_encoder_atomic_check()
152 * that on Tegra20 there's only a single clock dedicated to display in tegra_rgb_encoder_atomic_check()
154 * be used to independently drive a second output (pll_d2_out0). in tegra_rgb_encoder_atomic_check()
156 * As a way to support multiple outputs on Tegra20 as well, pll_p is in tegra_rgb_encoder_atomic_check()
161 * The best we can do at this point is to use the shift clock divider in tegra_rgb_encoder_atomic_check()
167 * Set display controller clock to x2 of PCLK in order to in tegra_rgb_encoder_atomic_check()
173 div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2; in tegra_rgb_encoder_atomic_check()
177 err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent, in tegra_rgb_encoder_atomic_check()
180 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); in tegra_rgb_encoder_atomic_check()
193 int tegra_dc_rgb_probe(struct tegra_dc *dc) in tegra_dc_rgb_probe() argument
199 np = of_get_child_by_name(dc->dev->of_node, "rgb"); in tegra_dc_rgb_probe()
201 return -ENODEV; in tegra_dc_rgb_probe()
203 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL); in tegra_dc_rgb_probe()
205 return -ENOMEM; in tegra_dc_rgb_probe()
207 rgb->output.dev = dc->dev; in tegra_dc_rgb_probe()
208 rgb->output.of_node = np; in tegra_dc_rgb_probe()
209 rgb->dc = dc; in tegra_dc_rgb_probe()
211 err = tegra_output_probe(&rgb->output); in tegra_dc_rgb_probe()
215 rgb->clk = devm_clk_get(dc->dev, NULL); in tegra_dc_rgb_probe()
216 if (IS_ERR(rgb->clk)) { in tegra_dc_rgb_probe()
217 dev_err(dc->dev, "failed to get clock\n"); in tegra_dc_rgb_probe()
218 return PTR_ERR(rgb->clk); in tegra_dc_rgb_probe()
221 rgb->clk_parent = devm_clk_get(dc->dev, "parent"); in tegra_dc_rgb_probe()
222 if (IS_ERR(rgb->clk_parent)) { in tegra_dc_rgb_probe()
223 dev_err(dc->dev, "failed to get parent clock\n"); in tegra_dc_rgb_probe()
224 return PTR_ERR(rgb->clk_parent); in tegra_dc_rgb_probe()
227 err = clk_set_parent(rgb->clk, rgb->clk_parent); in tegra_dc_rgb_probe()
229 dev_err(dc->dev, "failed to set parent clock: %d\n", err); in tegra_dc_rgb_probe()
233 rgb->pll_d_out0 = clk_get_sys(NULL, "pll_d_out0"); in tegra_dc_rgb_probe()
234 if (IS_ERR(rgb->pll_d_out0)) { in tegra_dc_rgb_probe()
235 err = PTR_ERR(rgb->pll_d_out0); in tegra_dc_rgb_probe()
236 dev_err(dc->dev, "failed to get pll_d_out0: %d\n", err); in tegra_dc_rgb_probe()
240 if (dc->soc->has_pll_d2_out0) { in tegra_dc_rgb_probe()
241 rgb->pll_d2_out0 = clk_get_sys(NULL, "pll_d2_out0"); in tegra_dc_rgb_probe()
242 if (IS_ERR(rgb->pll_d2_out0)) { in tegra_dc_rgb_probe()
243 err = PTR_ERR(rgb->pll_d2_out0); in tegra_dc_rgb_probe()
244 dev_err(dc->dev, "failed to get pll_d2_out0: %d\n", err); in tegra_dc_rgb_probe()
249 dc->rgb = &rgb->output; in tegra_dc_rgb_probe()
254 void tegra_dc_rgb_remove(struct tegra_dc *dc) in tegra_dc_rgb_remove() argument
258 if (!dc->rgb) in tegra_dc_rgb_remove()
261 rgb = to_rgb(dc->rgb); in tegra_dc_rgb_remove()
262 clk_put(rgb->pll_d2_out0); in tegra_dc_rgb_remove()
263 clk_put(rgb->pll_d_out0); in tegra_dc_rgb_remove()
265 tegra_output_remove(dc->rgb); in tegra_dc_rgb_remove()
266 dc->rgb = NULL; in tegra_dc_rgb_remove()
269 int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc) in tegra_dc_rgb_init() argument
271 struct tegra_output *output = dc->rgb; in tegra_dc_rgb_init()
275 if (!dc->rgb) in tegra_dc_rgb_init()
276 return -ENODEV; in tegra_dc_rgb_init()
278 drm_simple_encoder_init(drm, &output->encoder, DRM_MODE_ENCODER_LVDS); in tegra_dc_rgb_init()
279 drm_encoder_helper_add(&output->encoder, in tegra_dc_rgb_init()
283 * Wrap directly-connected panel into DRM bridge in order to let in tegra_dc_rgb_init()
284 * DRM core to handle panel for us. in tegra_dc_rgb_init()
286 if (output->panel) { in tegra_dc_rgb_init()
287 output->bridge = devm_drm_panel_bridge_add(output->dev, in tegra_dc_rgb_init()
288 output->panel); in tegra_dc_rgb_init()
289 if (IS_ERR(output->bridge)) { in tegra_dc_rgb_init()
290 dev_err(output->dev, in tegra_dc_rgb_init()
291 "failed to wrap panel into bridge: %pe\n", in tegra_dc_rgb_init()
292 output->bridge); in tegra_dc_rgb_init()
293 return PTR_ERR(output->bridge); in tegra_dc_rgb_init()
296 output->panel = NULL; in tegra_dc_rgb_init()
301 * for converting up to 28 LCD LVTTL lanes into 5/4 LVDS lanes that in tegra_dc_rgb_init()
302 * go to display panel's receiver. in tegra_dc_rgb_init()
304 * Encoder usually have a power-down control which needs to be enabled in tegra_dc_rgb_init()
305 * in order to transmit data to the panel. Historically devices that in tegra_dc_rgb_init()
306 * use an older device-tree version didn't model the bridge, assuming in tegra_dc_rgb_init()
308 * to model LVDS encoder properly. in tegra_dc_rgb_init()
310 * Newer device-trees utilize LVDS encoder bridge, which provides in tegra_dc_rgb_init()
313 * For older device-trees we wrapped panel into the panel-bridge. in tegra_dc_rgb_init()
315 if (output->bridge) { in tegra_dc_rgb_init()
316 err = drm_bridge_attach(&output->encoder, output->bridge, in tegra_dc_rgb_init()
321 connector = drm_bridge_connector_init(drm, &output->encoder); in tegra_dc_rgb_init()
323 dev_err(output->dev, in tegra_dc_rgb_init()
324 "failed to initialize bridge connector: %pe\n", in tegra_dc_rgb_init()
329 drm_connector_attach_encoder(connector, &output->encoder); in tegra_dc_rgb_init()
334 dev_err(output->dev, "failed to initialize output: %d\n", err); in tegra_dc_rgb_init()
339 * Other outputs can be attached to either display controller. The RGB in tegra_dc_rgb_init()
343 output->encoder.possible_crtcs = drm_crtc_mask(&dc->base); in tegra_dc_rgb_init()
348 int tegra_dc_rgb_exit(struct tegra_dc *dc) in tegra_dc_rgb_exit() argument
350 if (dc->rgb) in tegra_dc_rgb_exit()
351 tegra_output_exit(dc->rgb); in tegra_dc_rgb_exit()